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214 lines
4.6 KiB
Verilog
214 lines
4.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Lane Brooks.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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reg [31:0] state; initial state=0;
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wire A = state[0];
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wire OE = state[1];
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wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
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wire [3:0] Z10;
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wire Z11;
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Test1 test1(/*AUTOINST*/
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// Inouts
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.Z1 (Z1),
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// Inputs
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.OE (OE),
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.A (A));
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Test2 test2(/*AUTOINST*/
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// Inouts
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.Z2 (Z2),
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// Inputs
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.OE (OE),
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.A (A));
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Test3 test3(/*AUTOINST*/
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// Inouts
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.Z3 (Z3),
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// Inputs
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.OE (OE),
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.A (A));
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Test4 test4(/*AUTOINST*/
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// Outputs
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.Z4 (Z4),
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// Inouts
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.Z5 (Z5));
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Test5 test5(/*AUTOINST*/
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// Inouts
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.Z6 (Z6),
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.Z7 (Z7),
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.Z8 (Z8),
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.Z9 (Z9),
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// Inputs
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.OE (OE));
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Test6 test6(/*AUTOINST*/
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// Inouts
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.Z10 (Z10[3:0]),
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// Inputs
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.OE (OE));
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Test7 test7(/*AUTOINST*/
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// Outputs
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.Z11 (Z11),
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// Inputs
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.state (state[2:0]));
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always @(posedge clk) begin
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state <= state + 1;
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`ifdef TEST_VERBOSE
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$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n",
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$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11);
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`endif
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if(state == 0) begin
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if(Z1 !== 1'b1) $stop; // tests pullups
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if(Z2 !== 1'b1) $stop;
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if(Z3 !== 1'b1) $stop;
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`ifndef VERILATOR
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if(Z4 !== 1'b1) $stop;
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`endif
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if(Z5 !== 1'b1) $stop;
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if(Z6 !== 1'b1) $stop;
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if(Z7 !== 1'b0) $stop;
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if(Z8 !== 1'b0) $stop;
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if(Z9 !== 1'b1) $stop;
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if(Z10 !== 4'b0001) $stop;
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if(Z11 !== 1'b0) $stop;
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end
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else if(state == 1) begin
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if(Z1 !== 1'b1) $stop; // tests pullup
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if(Z2 !== 1'b1) $stop;
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if(Z3 !== 1'b1) $stop;
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`ifndef VERILATOR
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if(Z4 !== 1'b1) $stop;
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`endif
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if(Z5 !== 1'b1) $stop;
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if(Z6 !== 1'b1) $stop;
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if(Z7 !== 1'b0) $stop;
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if(Z8 !== 1'b0) $stop;
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if(Z9 !== 1'b1) $stop;
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if(Z10 !== 4'b0001) $stop;
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if(Z11 !== 1'b1) $stop;
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end
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else if(state == 2) begin
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if(Z1 !== 1'b0) $stop; // tests output driver low
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if(Z2 !== 1'b0) $stop;
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if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
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`ifndef VERILATOR
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if(Z4 !== 1'b1) $stop;
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`endif
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if(Z5 !== 1'b1) $stop;
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if(Z6 !== 1'b0) $stop;
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if(Z7 !== 1'b1) $stop;
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if(Z8 !== 1'b1) $stop;
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if(Z9 !== 1'b0) $stop;
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if(Z10 !== 4'b0010) $stop;
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//if(Z11 !== 1'bx) $stop; // Doesn't matter
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end
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else if(state == 3) begin
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if(Z1 !== 1'b1) $stop; // tests output driver high
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if(Z2 !== 1'b1) $stop;
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if(Z3 !== 1'b1) $stop;
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`ifndef VERILATOR
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if(Z4 !== 1'b1) $stop;
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`endif
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if(Z5 !== 1'b1) $stop;
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if(Z6 !== 1'b0) $stop;
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if(Z7 !== 1'b1) $stop;
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if(Z8 !== 1'b1) $stop;
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if(Z9 !== 1'b0) $stop;
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if(Z10 !== 4'b0010) $stop;
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if(Z11 !== 1'b1) $stop;
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end
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else if(state == 4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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pullup(Z1);
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pullup(Z2);
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pullup(Z3);
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pullup(Z4);
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pullup(Z5);
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pullup(Z6);
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pulldown(Z7);
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pullup(Z8);
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pulldown(Z9);
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pulldown pd10[3:0] (Z10);
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endmodule
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module Test1(input OE, input A, inout Z1);
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assign Z1 = (OE) ? A : 1'bz;
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endmodule
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module Test2(input OE, input A, inout Z2);
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assign Z2 = (OE) ? A : 1'bz;
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endmodule
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// mixed low-Z and tristate
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module Test3(input OE, input A, inout Z3);
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assign Z3 = (OE) ? A : 1'bz;
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assign Z3 = 1'b1;
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endmodule
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// floating output and inout
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`ifndef VERILATOR
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// Note verilator doesn't know to make Z4 a tristate unless marked an inout
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`endif
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module Test4(output Z4, inout Z5);
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endmodule
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// AND gate tristates
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module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
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assign Z6 = (OE) ? 1'b0 : 1'bz;
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assign Z7 = (OE) ? 1'b1 : 1'bz;
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assign Z8 = (OE) ? 1'bz : 1'b0;
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assign Z9 = (OE) ? 1'bz : 1'b1;
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endmodule
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// AND gate tristates
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module Test6(input OE, inout [3:0] Z10);
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wire [1:0] i;
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Test6a a (.OE(OE), .Z({Z10[0],Z10[1]}));
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Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]}));
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endmodule
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module Test6a(input OE, inout [1:0] Z);
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assign Z = (OE) ? 2'b01 : 2'bzz;
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endmodule
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module Test7(input [2:0] state, output reg Z11);
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always @(*) begin
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casez (state)
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3'b000: Z11 = 1'b0;
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3'b0?1: Z11 = 1'b1;
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default: Z11 = 1'bx;
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endcase
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end
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endmodule
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// This is not implemented yet
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//module Test3(input OE, input A, inout Z3);
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// always @(*) begin
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// if(OE) begin
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// Z3 = A;
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// end else begin
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// Z3 = 1'bz;
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// end
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// end
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//endmodule
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