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27 lines
582 B
Verilog
27 lines
582 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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Test0 t0 (.val0('0));
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Test1 t1 (.val1('0));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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package params;
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parameter P = 7;
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endpackage
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module Test0 (val0);
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parameter Z = 1;
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input [Z : 0] val0;
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endmodule
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module Test1 (val1);
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input logic [params::P : 0] val1; // Fully qualified parameter
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endmodule
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