mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-12-23 18:31:08 +00:00
166 lines
5.9 KiB
JavaScript
166 lines
5.9 KiB
JavaScript
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var assert = require('assert');
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var fs = require('fs');
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var wtu = require('./workertestutils.js');
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createTestDOM();
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var emu = require('gen/common/emu.js');
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var verilog = require('gen/platform/verilog.js');
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var VerilogPlatform = emu.PLATFORMS['verilog'];
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Object.assign(global, verilog); // copy global VL_* properties
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// TODO: must define $
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function loadPlatform(msg) {
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var platform = new VerilogPlatform();
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platform.resume = function() { }; // prevent resume after reset
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try {
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//console.log(msg.output.ports);
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//console.log(msg.output.signals);
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platform.loadROM("ROM", msg.output);
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platform.loadROM("ROM", msg.output);
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platform.loadROM("ROM", msg.output);
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verilog.vl_finished = verilog.vl_stopped = false;
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for (var i=0; i<100000 && !(verilog.vl_finished||verilog.vl_stopped); i++) {
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platform.tick();
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}
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assert.ok(!verilog.vl_stopped);
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var state = platform.saveState();
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platform.reset();
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platform.loadState(state);
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assert.deepEqual(state, platform.saveState());
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} catch (e) {
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//platform.printErrorCodeContext(e, msg.output.code);
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//console.log(msg.intermediate.listing);
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console.log(msg.output.code);
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console.log(e);
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throw e;
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}
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return platform;
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}
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function testPerf(msg) {
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var platform = new VerilogPlatform();
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platform.loadROM("ROM", msg.output);
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var niters = 5000000;
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console.time("before");
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for (var i=0; i<niters; i++)
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platform.tick();
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console.timeEnd("before");
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var state = platform.saveState();
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platform.reset();
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platform.loadState(state);
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console.time("after");
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for (var i=0; i<niters; i++)
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platform.tick();
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console.timeEnd("after");
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return platform;
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}
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function compileVerilator(filename, code, callback, nerrors) {
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global.postMessage = function(msg) {
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if (msg.errors && msg.errors.length) {
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console.log(msg.errors);
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assert.equal(nerrors||0, msg.errors.length, "errors");
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} else {
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assert.equal(nerrors||0, 0, "errors");
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loadPlatform(msg);
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//testPerf(msg);
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if (filename.indexOf('t_') >= 0) {
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//assert.ok(verilog.vl_finished);
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}
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}
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callback(null, msg);
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};
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global.onmessage({
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data:{code:code, platform:'verilog', tool:'verilator', path:'main.v'}
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});
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}
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function testVerilator(filename, disables, nerrors) {
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it('should translate '+filename, function(done) {
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var csource = ab2str(fs.readFileSync(filename));
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for (var i=0; i<(disables||[]).length; i++)
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csource = "/* verilator lint_off " + disables[i] + " */\n" + csource;
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compileVerilator(filename, csource, done, nerrors||0);
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});
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}
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describe('Verilog Worker', function() {
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testVerilator('presets/verilog/hvsync_generator.v');
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testVerilator('presets/verilog/lfsr.v');
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testVerilator('presets/verilog/ram.v');
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// TODO: how to include files?
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//testVerilator('test/cli/verilog/t_tri_gate.v');
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testVerilator('test/cli/verilog/t_tri_gen.v', ['UNDRIVEN']);
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testVerilator('test/cli/verilog/t_tri_graph.v', ['UNDRIVEN']);
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testVerilator('test/cli/verilog/t_tri_ifbegin.v', ['UNDRIVEN']);
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testVerilator('test/cli/verilog/t_tri_inout.v');
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testVerilator('test/cli/verilog/t_tri_inout2.v');
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testVerilator('test/cli/verilog/t_tri_pullup.v', ['UNDRIVEN']);
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testVerilator('test/cli/verilog/t_tri_select_unsized.v', ['WIDTH']);
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testVerilator('test/cli/verilog/t_tri_unconn.v', ['PINCONNECTEMPTY']);
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testVerilator('test/cli/verilog/t_tri_various.v', ['UNDRIVEN']);
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/* TODO: fix tests
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testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_alw_combdly.v');
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testVerilator('test/cli/verilog/t_math_const.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_clk_first.v', ['UNDRIVEN','SYNCASYNCNET']);
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testVerilator('test/cli/verilog/t_clk_2in.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_order_comboclkloop.v');
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*/
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testVerilator('test/cli/verilog/t_gen_alw.v');
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testVerilator('test/cli/verilog/t_case_huge_sub3.v');
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//testVerilator('test/cli/verilog/t_order.v');
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//testVerilator('test/cli/verilog/t_order_2d.v');
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//testVerilator('test/cli/verilog/t_order_a.v');
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//testVerilator('test/cli/verilog/t_order_b.v');
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//testVerilator('test/cli/verilog/t_order_clkinst.v');
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//testVerilator('test/cli/verilog/t_order_comboloop.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_order_first.v');
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//testVerilator('test/cli/verilog/t_order_loop_bad.v', ['BLKSEQ'], 10);
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testVerilator('test/cli/verilog/t_order_multialways.v');
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testVerilator('test/cli/verilog/t_order_multidriven.v', ['UNDRIVEN']);
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//testVerilator('test/cli/verilog/t_order_quad.v');
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testVerilator('test/cli/verilog/t_order_wireloop.v', ['UNOPT']);
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testVerilator('test/cli/verilog/t_mem.v');
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testVerilator('test/cli/verilog/t_alw_dly.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_alw_split.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_alw_splitord.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_array_compare.v');
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testVerilator('test/cli/verilog/t_math_arith.v', ['BLKSEQ']);
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//testVerilator('test/cli/verilog/t_math_div.v');
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testVerilator('test/cli/verilog/t_math_div0.v');
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testVerilator('test/cli/verilog/t_clk_powerdn.v', ['BLKSEQ','SYNCASYNCNET']);
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//testVerilator('test/cli/verilog/t_clk_latchgate.v', ['BLKSEQ']);
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//testVerilator('test/cli/verilog/t_clk_latch.v');
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//testVerilator('test/cli/verilog/t_clk_gater.v', ['BLKSEQ']);
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testVerilator('test/cli/verilog/t_clk_dsp.v');
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testVerilator('test/cli/verilog/t_clk_dpulse.v');
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testVerilator('test/cli/verilog/t_clk_condflop_nord.v');
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testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']);
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testVerilator('presets/verilog/hvsync_generator.v');
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testVerilator('presets/verilog/cpu6502.v');
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/*
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it('should compile verilog example', function(done) {
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var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v'));
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compileVerilator(csource, done);
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});
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*/
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});
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