mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-08-17 03:29:09 +00:00
33 lines
602 B
Verilog
33 lines
602 B
Verilog
|
|
`include "hvsync_generator.v"
|
|
|
|
/*
|
|
A simple test pattern using the hvsync_generator module.
|
|
*/
|
|
|
|
module test_hvsync_top(clk, reset, hsync, vsync, rgb);
|
|
|
|
input clk, reset;
|
|
output hsync, vsync;
|
|
output [2:0] rgb;
|
|
wire display_on;
|
|
wire [8:0] hpos;
|
|
wire [8:0] vpos;
|
|
|
|
hvsync_generator hvsync_gen(
|
|
.clk(clk),
|
|
.reset(0),
|
|
.hsync(hsync),
|
|
.vsync(vsync),
|
|
.display_on(display_on),
|
|
.hpos(hpos),
|
|
.vpos(vpos)
|
|
);
|
|
|
|
wire r = display_on && (((hpos&7)==0) || ((vpos&7)==0));
|
|
wire g = display_on && vpos[4];
|
|
wire b = display_on && hpos[4];
|
|
assign rgb = {b,g,r};
|
|
|
|
endmodule
|