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8bitworkshop/presets/verilog/femto8.json

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{
"name":"femto8",
"vars":{
"reg":{"bits":2, "toks":["a", "b", "ip", "none"]},
"unop":{"bits":3, "toks":["zero","loada","inc","dec","asl","lsr","rol","ror"]},
"binop":{"bits":3, "toks":["or","and","xor","mov","add","sub","adc","sbb"]},
"const4":{"bits":4},
"imm8":{"bits":8}
},
"rules":[
{"fmt":"~binop ~reg,b", "bits":["00",1,"1",0]},
{"fmt":"~binop ~reg,#~imm8", "bits":["01",1,"1",0,2]},
{"fmt":"~binop ~reg,[b]", "bits":["11",1,"1",0]},
{"fmt":"~unop ~reg", "bits":["00",1,"0",0]},
{"fmt":"mov ~reg,[b]", "bits":["11",0,"1011"]},
{"fmt":"zero ~reg", "bits":["00",0,"1011"]},
{"fmt":"lda #~imm8", "bits":["01","00","1011",0]},
{"fmt":"ldb #~imm8", "bits":["01","01","1011",0]},
{"fmt":"jmp ~imm8", "bits":["01","10","1011",0]},
{"fmt":"sta ~const4", "bits":["1001",0]},
{"fmt":"bcc ~imm8", "bits":["1010","0001",0]},
{"fmt":"bcs ~imm8", "bits":["1010","0011",0]},
{"fmt":"bz ~imm8", "bits":["1010","1100",0]},
{"fmt":"bnz ~imm8", "bits":["1010","0100",0]},
{"fmt":"clc", "bits":["10001000"]},
{"fmt":"swapab", "bits":["10000001"]},
{"fmt":"reset", "bits":["10001111"]}
]
}