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8bitworkshop/presets/verilog/Makefile
2018-02-16 23:33:29 -06:00

8 lines
175 B
Makefile

check:
verilator --top-module frame_buffer_top --lint-only *.v
iverilog -tnull *.v
deps.dot:
grep \`include *.v | sed "s/:/ /g" | awk '{ print "\"" $1 "\" -> " $3 ";" }'