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59 lines
1.3 KiB
Verilog
59 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.cyc (cyc[31:0]));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test
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(
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input clk,
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input [31:0] cyc
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);
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`ifdef FAIL_ASSERT_1
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assert property (@(posedge clk) cyc==3)
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else $display("cyc != 3, cyc == %0d", cyc);
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assume property (@(posedge clk) cyc==3)
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else $display("cyc != 3, cyc == %0d", cyc);
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`endif
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`ifdef FAIL_ASSERT_2
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assert property (@(posedge clk) cyc!=3);
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assume property (@(posedge clk) cyc!=3);
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`endif
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assert property (@(posedge clk) cyc < 100);
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assume property (@(posedge clk) cyc < 100);
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restrict property (@(posedge clk) cyc==1); // Ignored in simulators
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// Unclocked is not supported:
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// assert property (cyc != 6);
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endmodule
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