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19 lines
575 B
Verilog
19 lines
575 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire ok = 1'b0;
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// verilator lint_off PINNOCONNECT
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// verilator lint_off PINCONNECTEMPTY
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sub sub (.ok(ok), , .nc());
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// verilator lint_on PINCONNECTEMPTY
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// verilator lint_on PINNOCONNECT
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endmodule
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module sub (input ok, input none, input nc);
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initial if (ok && none && nc) begin end // No unused warning
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endmodule
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