mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-12-01 13:50:30 +00:00
14 lines
339 B
Verilog
14 lines
339 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t_multitop1s;
|
|
initial $display("In '%m'");
|
|
endmodule
|
|
|
|
module in_subfile;
|
|
initial $display("In '%m'");
|
|
endmodule
|