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51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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reg [63:0] inwide;
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reg [39:0] addr;
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write ("%x %x\n", cyc, addr);
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`endif
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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addr <= 40'h12_3456_7890;
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end
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if (cyc==2) begin
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if (addr !== 40'h1234567890) $stop;
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addr[31:0] <= 32'habcd_efaa;
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end
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if (cyc==3) begin
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if (addr !== 40'h12abcdefaa) $stop;
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addr[39:32] <= 8'h44;
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inwide <= 64'hffeeddcc_11334466;
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end
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if (cyc==4) begin
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if (addr !== 40'h44abcdefaa) $stop;
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addr[31:0] <= inwide[31:0];
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end
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if (cyc==5) begin
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if (addr !== 40'h4411334466) $stop;
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$display ("Flip [%x]\n", inwide[3:0]);
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addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
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end
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if (cyc==6) begin
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if (addr !== 40'h4411334426) $stop;
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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