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11 lines
311 B
Verilog
11 lines
311 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_waiveroutput;
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reg width_warn = 2'b11; // Width warning - must be line 18
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endmodule
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