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18 lines
363 B
Verilog
18 lines
363 B
Verilog
module gates(clk, out_not, out_and, out_or, out_xor, in);
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input clk;
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output out_not, out_and, out_or, out_xor;
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output reg [3:0] in;
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not U1(out_not,in[0]);
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and U2(out_and,in[0],in[1],in[2],in[3]);
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or U3(out_or,in[0],in[1],in[2],in[3]);
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xor U4(out_xor,in[0],in[1],in[2]);
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always @(posedge clk) begin
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in <= in + 1;
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end
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endmodule
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