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73 lines
1.5 KiB
Verilog
73 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [7:0] crc;
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reg [2:0] sum;
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wire [2:0] in = crc[2:0];
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wire [2:0] out;
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MxN_pipeline pipe (in, out, clk);
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
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cyc <= cyc + 1;
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crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
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if (cyc==0) begin
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// Setup
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crc <= 8'hed;
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sum <= 3'h0;
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end
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else if (cyc>10 && cyc<90) begin
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sum <= {sum[1:0],sum[2]} ^ out;
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end
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else if (cyc==99) begin
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if (crc !== 8'b01110000) $stop;
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if (sum !== 3'h3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module dffn (q,d,clk);
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parameter BITS = 1;
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input [BITS-1:0] d;
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output reg [BITS-1:0] q;
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input clk;
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always @ (posedge clk) begin
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q <= d;
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end
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endmodule
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module MxN_pipeline (in, out, clk);
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parameter M=3, N=4;
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input [M-1:0] in;
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output [M-1:0] out;
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input clk;
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// Unsupported: Per-bit array instantiations with output connections to non-wires.
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//wire [M*(N-1):1] t;
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//dffn #(M) p[N:1] ({out,t},{t,in},clk);
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wire [M*(N-1):1] w;
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wire [M*N:1] q;
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dffn #(M) p[N:1] (q,{w,in},clk);
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assign {out,w} = q;
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endmodule
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