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142 lines
4.3 KiB
Verilog
142 lines
4.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
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`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
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module t (/*AUTOARG*/);
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bit fail;
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localparam signed [3:0] bug737_p1 = 4'b1000;
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wire [3:0] bug737_a = 4'b1010;
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reg [5:0] bug737_y;
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reg signed [3:0] w4_s;
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reg signed [4:0] w5_s;
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reg [3:0] w4_u;
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reg [4:0] w5_u;
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reg signed [8:0] w9_s;
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real r;
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initial begin
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// verilator lint_off WIDTH
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bug737_y = bug737_a + (bug737_p1 + 4'sb0);
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`checkh(bug737_y, 6'b010010); //bug737
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// 6u +[6u] 4s +[6s] 6s
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bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
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`checkh(bug737_y, 6'b010010); //bug737, getx 000010
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// 6u +[6u] 4s +[6s] 6s
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bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
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`checkh(bug737_y, 6'b010010); //ok
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bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
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`checkh(bug737_y, 6'b000010); //ok
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// v--- sign extends to 6-bits
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bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
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`checkh(bug737_y, 6'b000010); //ok
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// From t_math_signed_3
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w4_s = 4'sb1111 - 1'b1;
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`checkh(w4_s,33'he);
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w4_s = 4'sb1111 - 5'b00001;
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`checkh(w4_s,33'he);
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w4_s = 4'sb1111 - 1'sb1;
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`checkh(w4_s,4'h0);
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w5_s = 4'sb1111 - 1'sb1;
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`checkh(w5_s,4'h0);
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w4_s = 4'sb1111 - 4'sb1111;
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`checkh(w4_s,4'h0);
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w5_s = 4'sb1111 - 4'sb1111;
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`checkh(w5_s,5'h0);
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// The assign LHS being signed or unsigned does not matter per IEEE
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// The upper add being signed DOES matter propagating to lower
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w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add
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`checkh(w4_s,4'he);
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w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend
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`checkh(w4_s,4'h0);
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w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend
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`checkh(w4_s,4'he); // BUG, Verilator says 'h0
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w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS
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`checkh(w5_u, 5'b10000);
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w4_u = 4'b1111 + 4'b0001; // Normal case
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`checkh(w4_u, 4'b0000);
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// Another example of promotion, the add is 4 bits wide
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w4_u = 3'b111 + 3'b010;
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`checkh(w4_u, 4'b1001);
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//
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w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
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`checkh(w4_u, 4'sb1111);
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w4_s = 3'sb111 * 3'sb001; // Signed output
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`checkh(w4_s, 4'sb1111);
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w4_s = 3'b111 * 3'sb001; // Unsigned output
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`checkh(w4_s, 4'b0111);
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// Conditionals get width from parent; are assignment-like
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w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
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`checkh(w4_u, 4'b0100);
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w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
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`checkh(w4_u, 4'b0000);
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// If RHS is larger, that larger size is used
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w4_u = 5'b10000 / 5'b00100;
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`checkh(w4_u, 4'b0100);
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// bug754
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w5_u = 4'sb0010 << -2'sd1; // << 3
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`ifdef VCS
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`checkh(w5_u, 5'b00000); // VCS E-2014.03 bug
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`else
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`checkh(w5_u, 5'b10000); // VCS E-2014.03 bug
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`endif
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w5_u = 4'sb1000 << 0; // Sign extends
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`checkh(w5_u, 5'b11000);
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// Reals do not propagate to children
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r = 1.0 + ( 1 + (1 / 2));
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`checkf(r, 2.0);
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// Self determined sign extension
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r = $itor(3'sb111);
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`checkf(r, -1.0);
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// If any part of case is real, all is real
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case (22)
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22.0: ;
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22.1: $stop;
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default: $stop;
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endcase
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// bug759
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w5_u = { -4'sd7 };
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`checkh(w5_u, 5'b01001);
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w5_u = {2{ -2'sd1 }};
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`checkh(w5_u, 5'b01111);
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// Don't break concats....
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w5_u = {{0{1'b1}}, -4'sd7 };
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`checkh(w5_u, 5'b01001);
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w9_s = { -4'sd7, -4'sd7 };
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`checkh(w9_s, 9'b010011001);
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{w5_u, {w4_u}} = 9'b10101_1100;
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`checkh(w5_u, 5'b10101);
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`checkh(w4_u, 4'b1100);
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{w4_u} = 4'b1011;
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`checkh(w4_u, 4'b1011);
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if (fail) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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