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110 lines
2.4 KiB
Verilog
110 lines
2.4 KiB
Verilog
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`include "hvsync_generator.v"
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`include "cpu16.v"
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module frame_buffer_top(clk, reset, hsync, vsync, hpaddle, vpaddle,
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address_bus, to_cpu, from_cpu, write_enable,
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rgb
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);
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input clk, reset;
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input hpaddle, vpaddle;
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output hsync, vsync;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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output reg [3:0] rgb;
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reg [15:0] ram[0:32767]; // RAM (32768 x 16 bits)
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reg [15:0] rom[0:1023]; // ROM (1024 x 16 bits)
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// 16-bit CPU
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output wire [15:0] address_bus;
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output reg [15:0] to_cpu;
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output wire [15:0] from_cpu;
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output wire write_enable;
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CPU16 cpu(.clk(clk),
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.reset(reset),
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.hold(hold),
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.busy(busy),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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// CPU -> RAM write bus (synchronous)
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always @(posedge clk)
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if (write_enable) begin
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ram[address_bus[14:0]] <= from_cpu;
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end
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// RAM -> CPU read bus (asynchronous)
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always @(*)
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if (address_bus[15])
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to_cpu = rom[address_bus[9:0]];
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else
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to_cpu = ram[address_bus[14:0]];
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// video sync generator
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// CPU busy flags (not used here)
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reg hold = 0;
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wire busy;
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reg [12:0] vindex; // index into line array
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reg [15:0] vshift; // shift register with current word to output
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reg [3:0] palette[0:3] = '{0,1,4,7}; // simple palette array
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always @(posedge clk) begin
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if (display_on) begin
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// load next word from RAM every 8 pixels
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if (0 == hpos[2:0]) begin
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vshift <= ram[{2'b10,vindex}];
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vindex <= vindex + 1;
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end else
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vshift <= vshift << 2; // shift next pixel in 16-bit word
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// decode scanline RAM to RGB output
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rgb <= palette[vshift[15:14]];
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end else begin
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rgb <= 0; // set color to black
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if (vsync) vindex <= 0; // reset vindex every frame
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end;
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end
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// test program
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`ifdef EXT_INLINE_ASM
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initial begin
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rom = '{
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__asm
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.arch femto16
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.org 32768
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.len 1024
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Start:
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mov ax,cx ; ax = cx
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mov bx,#0 ; bx = #0
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Loop:
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mov [bx],ax ; ram[bx] = ax
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inc ax ; ax = ax + 1
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inc bx ; bx = bx + 1
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bnz Loop ; loop until bx is 0
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inc cx
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reset ; reset CPU
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__endasm
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};
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end
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`endif
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endmodule
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