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https://github.com/sehugg/8bitworkshop.git
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304 lines
7.4 KiB
Verilog
304 lines
7.4 KiB
Verilog
`ifndef ALU_H
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`define ALU_H
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// ALU operations
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`define OP_LOAD_A 4'h0
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`define OP_LOAD_B 4'h1
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`define OP_INC 4'h2
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`define OP_DEC 4'h3
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`define OP_ASL 4'h4
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`define OP_LSR 4'h5
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`define OP_ROL 4'h6
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`define OP_ROR 4'h7
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`define OP_OR 4'h8
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`define OP_AND 4'h9
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`define OP_XOR 4'ha
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`define OP_ZERO 4'hb
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`define OP_ADD 4'hc
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`define OP_SUB 4'hd
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`define OP_ADC 4'he
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`define OP_SBB 4'hf
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module ALU(A, B, Y, aluop, carry);
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parameter N = 8;
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input [N-1:0] A;
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input [N-1:0] B;
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output [N:0] Y;
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input [3:0] aluop;
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input carry;
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always @(*)
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case (aluop)
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// unary operations
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`OP_LOAD_A: Y = {1'b0, A};
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`OP_LOAD_B: Y = {1'b0, B};
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`OP_INC: Y = A + 1;
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`OP_DEC: Y = A - 1;
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// unary operations that generate and/or use carry
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`OP_ASL: Y = {A, 1'b0};
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`OP_LSR: Y = {A[0], 1'b0, A[N-1:1]};
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`OP_ROL: Y = {A, carry};
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`OP_ROR: Y = {A[0], carry, A[N-1:1]};
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// binary operations
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`OP_OR: Y = {1'b0, A | B};
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`OP_AND: Y = {1'b0, A & B};
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`OP_XOR: Y = {1'b0, A ^ B};
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`OP_ZERO: Y = 0;
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// binary operations that generate and/or use carry
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`OP_ADD: Y = A + B;
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`OP_SUB: Y = A - B;
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`OP_ADC: Y = A + B + (carry?1:0);
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`OP_SBB: Y = A - B - (carry?1:0);
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endcase
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endmodule
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/*
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Bits Description
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00ddaaaa A @ B -> dest
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01ddaaaa A @ immediate -> dest
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11ddaaaa A @ read [B] -> dest
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10000001 swap A <-> B
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1001nnnn A -> write [nnnn]
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1010tttt conditional branch
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dd = destination (00=A, 01=B, 10=IP, 11=none)
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aaaa = ALU operation (@ operator)
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nnnn = 4-bit constant
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tttt = flags test for conditional branch
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*/
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// destinations for COMPUTE instructions
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`define DEST_A 2'b00
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`define DEST_B 2'b01
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`define DEST_IP 2'b10
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`define DEST_NOP 2'b11
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// instruction macros
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`define I_COMPUTE(dest,op) { 2'b00, (dest), (op) }
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`define I_COMPUTE_IMM(dest,op) { 2'b01, (dest), (op) }
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`define I_COMPUTE_READB(dest,op) { 2'b11, (dest), (op) }
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`define I_CONST_IMM_A { 2'b01, `DEST_A, `OP_LOAD_B }
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`define I_CONST_IMM_B { 2'b01, `DEST_B, `OP_LOAD_B }
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`define I_JUMP_IMM { 2'b01, `DEST_IP, `OP_LOAD_B }
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`define I_STORE_A(addr) { 4'b1001, (addr) }
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`define I_BRANCH_IF(zv,zu,cv,cu) { 4'b1010, (zv), (zu), (cv), (cu) }
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`define I_CLEAR_CARRY { 8'b10001000 }
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`define I_SWAP_AB { 8'b10000001 }
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`define I_RESET { 8'b10111111 }
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// convenience macros
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`define I_ZERO_A `I_COMPUTE(`DEST_A, `OP_ZERO)
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`define I_ZERO_B `I_COMPUTE(`DEST_B, `OP_ZERO)
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`define I_BRANCH_IF_CARRY(carry) `I_BRANCH_IF(1'b0, 1'b0, carry, 1'b1)
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`define I_BRANCH_IF_ZERO(zero) `I_BRANCH_IF(zero, 1'b1, 1'b0, 1'b0)
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`define I_CLEAR_ZERO `I_COMPUTE(`DEST_NOP, `OP_ZERO)
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module CPU(clk, reset, address, data_in, data_out, write);
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input clk;
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input reset;
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output [7:0] address;
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input [7:0] data_in;
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output [7:0] data_out;
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output write;
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reg [7:0] IP;
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reg [7:0] A, B;
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reg [8:0] Y;
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reg [2:0] state;
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reg carry;
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reg zero;
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wire [1:0] flags = { zero, carry };
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reg [7:0] opcode;
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wire [3:0] aluop = opcode[3:0];
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wire [1:0] opdest = opcode[5:4];
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wire B_or_data = opcode[6];
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localparam S_RESET = 0;
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localparam S_SELECT = 1;
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localparam S_DECODE = 2;
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localparam S_COMPUTE = 3;
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localparam S_READ_IP = 4;
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ALU alu(
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.A(A),
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.B(B_or_data ? data_in : B),
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.Y(Y),
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.aluop(aluop),
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.carry(carry));
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always @(posedge clk)
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if (reset) begin
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state <= 0;
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write <= 0;
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end else begin
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case (state)
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// state 0: reset
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S_RESET: begin
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IP <= 8'h80;
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write <= 0;
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state <= S_SELECT;
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end
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// state 1: select opcode address
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S_SELECT: begin
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address <= IP;
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IP <= IP + 1;
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write <= 0;
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state <= S_DECODE;
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end
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// state 2: read/decode opcode
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S_DECODE: begin
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opcode <= data_in; // (only use opcode next cycle)
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casez (data_in)
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// ALU A + B -> dest
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8'b00??????: begin
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state <= S_COMPUTE;
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end
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// ALU A + immediate -> dest
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8'b01??????: begin
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address <= IP;
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IP <= IP + 1;
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state <= S_COMPUTE;
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end
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// ALU A + read [B] -> dest
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8'b11??????: begin
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address <= B;
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state <= S_COMPUTE;
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end
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// A -> write [nnnn]
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8'b1001????: begin
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address <= {4'b0, data_in[3:0]};
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data_out <= A;
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write <= 1;
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state <= S_SELECT;
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end
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// clear carry
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8'b10001000: begin
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carry <= 0;
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state <= S_SELECT;
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end
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// swap A,B
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8'b10000001: begin
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A <= B;
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B <= A;
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state <= S_SELECT;
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end
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// conditional branch
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8'b1010????: begin
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if (
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(data_in[0] && (data_in[1] == carry)) ||
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(data_in[2] && (data_in[3] == zero)))
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begin
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address <= IP;
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state <= S_READ_IP;
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end else begin
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state <= S_SELECT;
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end
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IP <= IP + 1; // skip immediate
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end
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// fall-through RESET
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default: begin
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state <= S_RESET; // reset
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end
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endcase
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end
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// state 3: compute ALU op and flags
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S_COMPUTE: begin
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// transfer ALU output to destination
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case (opdest)
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`DEST_A: A <= Y[7:0];
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`DEST_B: B <= Y[7:0];
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`DEST_IP: IP <= Y[7:0];
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`DEST_NOP: ;
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endcase
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// set carry for certain operations (4-7,12-15)
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if (aluop[2]) carry <= Y[8];
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// set zero flag
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zero <= ~|Y[7:0];
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// repeat CPU loop
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state <= S_SELECT;
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end
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// state 4: read new IP from memory (immediate mode)
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S_READ_IP: begin
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IP <= data_in;
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state <= S_SELECT;
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end
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endcase
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end
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endmodule
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module test_CPU_top(
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input clk,
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input reset,
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output [7:0] address_bus,
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output reg [7:0] to_cpu,
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output [7:0] from_cpu,
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output write_enable,
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output [7:0] IP,
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output [7:0] A,
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output [7:0] B,
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output zero,
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output carry
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);
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reg [7:0] ram[0:127];
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reg [7:0] rom[0:127];
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assign IP = cpu.IP;
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assign A = cpu.A;
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assign B = cpu.B;
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assign zero = cpu.zero;
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assign carry = cpu.carry;
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CPU cpu(.clk(clk),
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.reset(reset),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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always @(posedge clk)
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if (write_enable) begin
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ram[address_bus[6:0]] <= from_cpu;
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end
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always @(*)
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if (address_bus[7] == 0)
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to_cpu = ram[address_bus[6:0]];
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else
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to_cpu = rom[address_bus[6:0]];
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initial begin
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rom = '{
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`I_CLEAR_CARRY,
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`I_ZERO_A,
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`I_CONST_IMM_B,
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1,
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`I_COMPUTE(`DEST_A, `OP_ADC), // addr 4
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`I_SWAP_AB,
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`I_BRANCH_IF_CARRY(1'b0),
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4 + 'h80, // correct for ROM offset
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`I_STORE_A(4'd0),
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`I_RESET,
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// leftover elements
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0,
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0,0,0,0, 0,0
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};
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end
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endmodule
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`endif
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