2015-06-16 17:41:46 +00:00
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--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : BusMonCore.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity BusMonCore is
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generic (
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num_comparators : integer := 8;
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reg_width : integer := 46;
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fifo_width : integer := 72
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2015-06-16 17:41:46 +00:00
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);
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port (
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clock49 : in std_logic;
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2015-06-30 13:19:19 +00:00
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-- CPU Signals
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Addr : in std_logic_vector(15 downto 0);
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Data : in std_logic_vector(7 downto 0);
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Phi2 : in std_logic;
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Rd_n : in std_logic;
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Wr_n : in std_logic;
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2015-06-30 13:19:19 +00:00
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RdIO_n : in std_logic;
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WrIO_n : in std_logic;
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Sync : in std_logic;
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Rdy : out std_logic;
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2015-06-27 10:07:58 +00:00
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nRSTin : in std_logic;
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nRSTout : out std_logic;
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2015-06-28 21:17:32 +00:00
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CountCycle : in std_logic;
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2015-06-30 13:19:19 +00:00
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-- CPU Registers
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-- unused in pure bus monitor mode
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Regs : in std_logic_vector(255 downto 0);
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-- CPU Memory Read/Write
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-- unused in pure bus monitor mode
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2015-06-29 13:43:20 +00:00
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RdMemOut : out std_logic;
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WrMemOut : out std_logic;
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RdIOOut : out std_logic;
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WrIOOut : out std_logic;
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AddrOut : out std_logic_vector(15 downto 0);
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DataOut : out std_logic_vector(7 downto 0);
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DataIn : in std_logic_vector(7 downto 0);
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Done : in std_logic;
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2015-06-27 10:07:58 +00:00
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-- Single Step interface
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SS_Single : out std_logic;
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SS_Step : out std_logic;
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2015-06-16 17:41:46 +00:00
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- HD44780 LCD
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lcd_rs : out std_logic;
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lcd_rw : out std_logic;
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lcd_e : out std_logic;
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lcd_db : inout std_logic_vector(7 downto 4);
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-- AVR Serial Port
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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nsw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end BusMonCore;
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architecture behavioral of BusMonCore is
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2015-06-20 11:30:18 +00:00
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signal clock_avr : std_logic;
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signal nrst_avr : std_logic;
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signal lcd_rw_int : std_logic;
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signal lcd_db_in : std_logic_vector(7 downto 4);
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signal lcd_db_out : std_logic_vector(7 downto 4);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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signal mux : std_logic_vector(7 downto 0);
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signal muxsel : std_logic_vector(5 downto 0);
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signal cmd_edge : std_logic;
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signal cmd_edge1 : std_logic;
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signal cmd_edge2 : std_logic;
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signal cmd : std_logic_vector(4 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal Data1 : std_logic_vector(7 downto 0);
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signal cycleCount : std_logic_vector(23 downto 0);
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signal cycleCount_inst : std_logic_vector(23 downto 0);
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signal single : std_logic;
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signal reset : std_logic;
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signal step : std_logic;
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signal bw_status : std_logic_vector(3 downto 0);
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signal bw_status1 : std_logic_vector(3 downto 0);
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2015-06-22 17:11:11 +00:00
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signal auto_inc : std_logic;
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2015-06-20 11:30:18 +00:00
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signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
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signal brkpt_enable : std_logic;
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signal brkpt_active : std_logic;
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signal brkpt_active1 : std_logic;
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signal watch_active : std_logic;
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signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_empty : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_wr : std_logic;
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signal fifo_rst : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal io_rd : std_logic;
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signal io_wr : std_logic;
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signal addr_dout_reg : std_logic_vector(23 downto 0);
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signal din_reg : std_logic_vector(7 downto 0);
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signal Rdy_int : std_logic;
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begin
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2015-07-02 14:35:05 +00:00
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inst_dcm0 : entity work.DCM0 port map(
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CLKIN_IN => clock49,
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CLK0_OUT => clock_avr,
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CLK0_OUT1 => open,
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CLK2X_OUT => open
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);
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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dy_clock => clock49,
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dy_rst_n => '1',
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dy_data => dy_data,
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dy_update => '1',
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dy_frame => open,
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dy_frameend => open,
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dy_frameend_c => open,
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dy_pwm => "1010",
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dy_counter => dy_counter,
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dy_sclk => tdin,
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dy_ser => tcclk,
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dy_rclk => tmosi
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);
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Inst_AVR8: entity work.AVR8 port map(
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clk16M => clock_avr,
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nrst => nrst_avr,
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portain(0) => '0',
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portain(1) => '0',
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portain(2) => '0',
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portain(3) => '0',
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portain(4) => lcd_db_in(4),
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portain(5) => lcd_db_in(5),
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portain(6) => lcd_db_in(6),
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portain(7) => lcd_db_in(7),
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portaout(0) => lcd_rs,
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portaout(1) => lcd_rw_int,
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portaout(2) => lcd_e,
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portaout(3) => open,
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portaout(4) => lcd_db_out(4),
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portaout(5) => lcd_db_out(5),
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portaout(6) => lcd_db_out(6),
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portaout(7) => lcd_db_out(7),
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-- Command Port
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portbin(0) => '0',
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portbin(1) => '0',
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portbin(2) => '0',
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portbin(3) => '0',
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portbin(4) => '0',
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portbin(5) => '0',
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portbin(6) => '0',
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portbin(7) => '0',
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portbout(0) => cmd(0),
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portbout(1) => cmd(1),
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portbout(2) => cmd(2),
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portbout(3) => cmd(3),
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portbout(4) => cmd(4),
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portbout(5) => cmd_edge,
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portbout(6) => open,
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portbout(7) => open,
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-- Status Port
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portdin(0) => '0',
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portdin(1) => '0',
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portdin(2) => '0',
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portdin(3) => '0',
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portdin(4) => '0',
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portdin(5) => '0',
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portdin(6) => sw1,
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portdin(7) => not fifo_empty,
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portdout(0) => muxsel(0),
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portdout(1) => muxsel(1),
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portdout(2) => muxsel(2),
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portdout(3) => muxsel(3),
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portdout(4) => muxsel(4),
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portdout(5) => muxsel(5),
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portdout(6) => open,
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portdout(7) => open,
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-- Mux Port
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portein => mux,
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porteout => open,
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spi_mosio => open,
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spi_scko => open,
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spi_misoi => '0',
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rxd => avr_RxD,
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txd => avr_TxD
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);
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WatchEvents_inst : entity work.WatchEvents port map(
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clk => Phi2,
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srst => fifo_rst,
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din => fifo_din,
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wr_en => fifo_wr,
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rd_en => fifo_rd,
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dout => fifo_dout,
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full => open,
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empty => fifo_empty
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);
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2015-06-20 11:30:18 +00:00
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-- The fifo is writen the cycle after the break point
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-- Addr1 is the address bus delayed by 1 cycle
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-- DataWr1 is the data being written delayed by 1 cycle
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-- DataRd is the data being read, that is already one cycle late
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-- bw_state1(1) is 1 for writes, and 0 for reads
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fifo_din <= cycleCount_inst & "0000" & bw_status1 & Data1 & Addr1 & addr_inst;
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lcd_rw <= lcd_rw_int;
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lcd_db <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
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lcd_db_in <= lcd_db;
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led3 <= not trig(0); -- red
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led6 <= not trig(1); -- red
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led8 <= not brkpt_active; -- green
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nrst_avr <= nsw2;
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-- OHO DY1 Display for Testing
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dy_data(0) <= hex & "0000" & Addr(3 downto 0);
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dy_data(1) <= hex & "0000" & Addr(7 downto 4);
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dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
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mux <= addr_inst(7 downto 0) when muxsel = 0 else
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addr_inst(15 downto 8) when muxsel = 1 else
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2015-06-20 11:30:18 +00:00
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din_reg when muxsel = 2 else
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cycleCount(23 downto 16) when muxsel = 3 else
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cycleCount(7 downto 0) when muxsel = 4 else
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cycleCount(15 downto 8) when muxsel = 5 else
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fifo_dout(7 downto 0) when muxsel = 6 else
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fifo_dout(15 downto 8) when muxsel = 7 else
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fifo_dout(23 downto 16) when muxsel = 8 else
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fifo_dout(31 downto 24) when muxsel = 9 else
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fifo_dout(39 downto 32) when muxsel = 10 else
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fifo_dout(47 downto 40) when muxsel = 11 else
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fifo_dout(55 downto 48) when muxsel = 12 else
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fifo_dout(63 downto 56) when muxsel = 13 else
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fifo_dout(71 downto 64) when muxsel = 14 else
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2015-06-28 18:42:25 +00:00
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Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
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2015-06-16 17:41:46 +00:00
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-- Combinatorial set of comparators to decode breakpoint/watch addresses
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2015-06-30 13:19:19 +00:00
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brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n)
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variable i : integer;
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variable reg_addr : std_logic_vector(15 downto 0);
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variable reg_mask : std_logic_vector(15 downto 0);
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2015-06-30 13:19:19 +00:00
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variable reg_mode_bmr : std_logic;
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variable reg_mode_bmw : std_logic;
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variable reg_mode_bir : std_logic;
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variable reg_mode_biw : std_logic;
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variable reg_mode_bx : std_logic;
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variable reg_mode_wmr : std_logic;
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variable reg_mode_wmw : std_logic;
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variable reg_mode_wir : std_logic;
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variable reg_mode_wiw : std_logic;
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variable reg_mode_wx : std_logic;
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variable reg_mode_all : std_logic_vector(9 downto 0);
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variable bactive : std_logic;
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variable wactive : std_logic;
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2015-06-20 11:30:18 +00:00
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variable status : std_logic_vector(3 downto 0);
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2015-06-16 17:41:46 +00:00
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variable trigval : std_logic;
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begin
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bactive := '0';
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wactive := '0';
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2015-06-20 11:30:18 +00:00
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status := (others => '0');
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2015-06-16 17:41:46 +00:00
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if (brkpt_enable = '1') then
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for i in 0 to num_comparators - 1 loop
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reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
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2015-06-19 15:10:07 +00:00
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reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
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2015-06-30 13:19:19 +00:00
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reg_mode_bmr := brkpt_reg(i * reg_width + 32);
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reg_mode_wmr := brkpt_reg(i * reg_width + 33);
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reg_mode_bmw := brkpt_reg(i * reg_width + 34);
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reg_mode_wmw := brkpt_reg(i * reg_width + 35);
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reg_mode_bir := brkpt_reg(i * reg_width + 36);
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reg_mode_wir := brkpt_reg(i * reg_width + 37);
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reg_mode_biw := brkpt_reg(i * reg_width + 38);
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reg_mode_wiw := brkpt_reg(i * reg_width + 39);
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reg_mode_bx := brkpt_reg(i * reg_width + 40);
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reg_mode_wx := brkpt_reg(i * reg_width + 41);
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reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
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trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
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if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
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2015-06-16 17:41:46 +00:00
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if (Sync = '1') then
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2015-06-30 13:19:19 +00:00
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if (reg_mode_bx = '1') then
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bactive := '1';
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status := "1000";
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elsif (reg_mode_wx = '1') then
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wactive := '1';
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status := "1001";
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end if;
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elsif (Rd_n = '0') then
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if (reg_mode_bmr = '1') then
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2015-06-16 17:41:46 +00:00
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bactive := '1';
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2015-06-30 13:19:19 +00:00
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status := "0000";
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elsif (reg_mode_wmr = '1') then
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wactive := '1';
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2015-06-20 11:30:18 +00:00
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status := "0001";
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-30 13:19:19 +00:00
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elsif (Wr_n = '0') then
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if (reg_mode_bmw = '1') then
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bactive := '1';
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status := "0010";
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elsif (reg_mode_wmw = '1') then
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2015-06-16 17:41:46 +00:00
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wactive := '1';
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2015-06-30 13:19:19 +00:00
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status := "0011";
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-30 13:19:19 +00:00
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elsif (RdIO_n = '0') then
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if (reg_mode_bir = '1') then
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bactive := '1';
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status := "0100";
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elsif (reg_mode_wir = '1') then
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wactive := '1';
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status := "0101";
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2015-06-27 10:07:58 +00:00
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end if;
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2015-06-30 13:19:19 +00:00
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elsif (WrIO_n = '0') then
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if (reg_mode_biw = '1') then
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bactive := '1';
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status := "0110";
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elsif (reg_mode_wiw = '1') then
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wactive := '1';
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status := "0111";
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-30 13:19:19 +00:00
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end if;
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2015-06-16 17:41:46 +00:00
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end if;
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end loop;
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end if;
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watch_active <= wactive;
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brkpt_active <= bactive;
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bw_status <= status;
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end process;
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2015-06-29 13:43:20 +00:00
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-- CPU Control Commands
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-- 0000x Enable/Disable single strpping
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2015-06-22 17:11:11 +00:00
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-- 0001x Enable/Disable breakpoints / watches
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2015-06-29 13:43:20 +00:00
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-- 0010x Load breakpoint / watch register
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-- 0011x Reset CPU
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-- 01000 Singe Step CPU
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-- 01001 Read FIFO
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-- 01010 Reset FIFO
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-- 01011 Unused
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-- 0110x Load address/data register
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-- 0111x Unused
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-- 10000 Read Memory
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-- 10001 Read Memory and Auto Inc Address
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-- 10010 Write Memory
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-- 10011 Write Memory and Auto Inc Address
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-- 10000 Read Memory
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-- 10001 Read Memory and Auto Inc Address
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-- 10010 Write Memory
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-- 10011 Write Memory and Auto Inc Address
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-- 1x1xx Unused
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2015-06-22 17:11:11 +00:00
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-- 11xxx Unused
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2015-06-29 13:43:20 +00:00
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2015-06-16 17:41:46 +00:00
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risingProcess: process (Phi2)
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begin
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if rising_edge(Phi2) then
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2015-06-20 11:30:18 +00:00
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-- Cycle counter, wraps every 16s at 1MHz
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2015-06-27 10:07:58 +00:00
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if (nRSTin = '0') then
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2015-06-20 11:30:18 +00:00
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cycleCount <= (others => '0');
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2015-06-28 21:17:32 +00:00
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elsif (CountCycle = '1') then
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2015-06-20 11:30:18 +00:00
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cycleCount <= cycleCount + 1;
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end if;
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2015-06-16 17:41:46 +00:00
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-- Command processing
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cmd_edge1 <= cmd_edge;
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cmd_edge2 <= cmd_edge1;
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fifo_rd <= '0';
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fifo_wr <= '0';
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fifo_rst <= '0';
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memory_rd <= '0';
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memory_wr <= '0';
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2015-06-29 13:43:20 +00:00
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io_rd <= '0';
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io_wr <= '0';
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2015-06-27 10:07:58 +00:00
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SS_Step <= '0';
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2015-06-16 17:41:46 +00:00
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if (cmd_edge2 = '0' and cmd_edge1 = '1') then
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "0000") then
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2015-06-16 17:41:46 +00:00
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single <= cmd(0);
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "0001") then
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2015-06-16 17:41:46 +00:00
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brkpt_enable <= cmd(0);
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "0010") then
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2015-06-16 17:41:46 +00:00
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brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "0110") then
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2015-06-16 17:41:46 +00:00
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addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "0011") then
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2015-06-16 17:41:46 +00:00
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reset <= cmd(0);
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 0) = "01001") then
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2015-06-16 17:41:46 +00:00
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fifo_rd <= '1';
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 0) = "01010") then
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2015-06-16 17:41:46 +00:00
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fifo_rst <= '1';
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "1000") then
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2015-06-16 17:41:46 +00:00
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memory_rd <= '1';
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2015-06-22 17:11:11 +00:00
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auto_inc <= cmd(0);
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-22 17:11:11 +00:00
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if (cmd(4 downto 1) = "1001") then
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2015-06-16 17:41:46 +00:00
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memory_wr <= '1';
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2015-06-22 17:11:11 +00:00
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auto_inc <= cmd(0);
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-29 13:43:20 +00:00
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if (cmd(4 downto 1) = "1010") then
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io_rd <= '1';
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auto_inc <= cmd(0);
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end if;
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if (cmd(4 downto 1) = "1011") then
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io_wr <= '1';
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auto_inc <= cmd(0);
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end if;
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-18 11:58:37 +00:00
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-- Auto increment the memory address reg the cycle after a rd/wr
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2015-06-28 18:42:25 +00:00
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if (auto_inc = '1' and Done = '1') then
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2015-06-18 11:58:37 +00:00
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addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
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end if;
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2015-06-16 17:41:46 +00:00
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-- Single Stepping
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2015-06-19 14:37:01 +00:00
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if (brkpt_active = '1') then
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single <= '1';
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end if;
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2015-06-22 17:11:11 +00:00
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if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "01000")) then
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2015-06-20 11:30:18 +00:00
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Rdy_int <= (not brkpt_active);
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2015-06-29 16:16:23 +00:00
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SS_Step <= (not brkpt_active);
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2015-06-16 17:41:46 +00:00
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else
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2015-06-20 11:30:18 +00:00
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Rdy_int <= (not Sync);
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2015-06-16 17:41:46 +00:00
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end if;
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2015-06-30 13:19:19 +00:00
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-- CPU Reset needs to be open collector
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2015-06-16 17:41:46 +00:00
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if (reset = '1') then
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2015-06-27 10:07:58 +00:00
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nRSTout <= '0';
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2015-06-16 17:41:46 +00:00
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else
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2015-06-27 10:07:58 +00:00
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nRSTout <= 'Z';
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2015-06-16 17:41:46 +00:00
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end if;
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-- Latch instruction address for the whole cycle
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if (Sync = '1') then
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addr_inst <= Addr;
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2015-06-20 11:30:18 +00:00
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cycleCount_inst <= cycleCount;
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2015-06-16 17:41:46 +00:00
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end if;
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-- Breakpoints and Watches written to the FIFO
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brkpt_active1 <= brkpt_active;
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bw_status1 <= bw_status;
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if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
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fifo_wr <= '1';
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2015-06-20 11:30:18 +00:00
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Addr1 <= Addr;
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2015-06-16 17:41:46 +00:00
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end if;
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end if;
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end process;
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fallingProcess: process (Phi2)
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begin
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if falling_edge(Phi2) then
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2015-06-20 11:30:18 +00:00
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-- Latch the data bus for use in watches
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Data1 <= Data;
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2015-06-16 17:41:46 +00:00
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-- Latch memory read in response to a read command
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2015-06-28 18:42:25 +00:00
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if (Done = '1') then
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2015-06-16 17:41:46 +00:00
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din_reg <= DataIn;
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end if;
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end if;
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end process;
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2015-06-20 11:30:18 +00:00
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Rdy <= Rdy_int;
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2015-06-29 13:43:20 +00:00
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RdMemOut <= memory_rd;
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WrMemOut <= memory_wr;
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RdIOOut <= io_rd;
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WrIOOut <= io_wr;
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2015-06-16 17:41:46 +00:00
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AddrOut <= addr_dout_reg(23 downto 8);
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DataOut <= addr_dout_reg(7 downto 0);
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2015-06-27 10:07:58 +00:00
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SS_Single <= single;
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2015-06-16 17:41:46 +00:00
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end behavioral;
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