2019-11-02 13:26:00 +00:00
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : Z80CpuMonGODIL.vhd
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-- /___/ /\ Timestamp : 14/10/2018
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: Z80CpuMonGODIL
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2019-11-02 14:50:43 +00:00
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--Device: XC3S500E
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2019-11-02 13:26:00 +00:00
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity Z80CpuMonGODIL is
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generic (
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num_comparators : integer := 8; -- default value correct for GODIL
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avr_prog_mem_size : integer := 1024 * 16 -- default value correct for GODIL
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);
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port (
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clock49 : in std_logic;
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-- Z80 Signals
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- Mode jumper, tie low to generate NOPs when paused
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mode : in std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Debugging signals
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test1 : out std_logic;
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test2 : out std_logic;
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test3 : out std_logic;
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test4 : out std_logic
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);
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end Z80CpuMonGODIL;
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architecture behavioral of Z80CpuMonGODIL is
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2019-11-04 09:31:56 +00:00
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signal sw_reset_avr : std_logic;
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signal sw_reset_cpu : std_logic;
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2019-11-02 13:26:00 +00:00
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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signal MREQ_n_int : std_logic;
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signal IORQ_n_int : std_logic;
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signal RD_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal tristate_n : std_logic;
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begin
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2019-11-04 09:31:56 +00:00
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sw_reset_cpu <= sw1;
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sw_reset_avr <= not sw2;
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2019-11-02 14:50:43 +00:00
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led3 <= not led_trig0;
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led6 <= not led_trig1;
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led8 <= not led_bkpt;
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2019-11-02 13:26:00 +00:00
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-- Tristateable output drivers
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MREQ_n <= 'Z' when tristate_n = '0' else MREQ_n_int;
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IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
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RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
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WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
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Addr <= (others => 'Z') when tristate_n = '0' else Addr_int;
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wrapper : entity work.Z80CpuMon
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generic map (
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2019-11-02 14:50:43 +00:00
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ClkMult => 10,
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ClkDiv => 31,
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ClkPer => 20.345,
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2019-11-02 13:26:00 +00:00
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map(
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2019-11-02 15:52:20 +00:00
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clock => clock49,
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2019-11-02 13:26:00 +00:00
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-- Z80 Signals
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RESET_n => RESET_n,
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CLK_n => CLK_n,
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WAIT_n => WAIT_n,
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INT_n => INT_n,
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NMI_n => NMI_n,
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BUSRQ_n => BUSRQ_n,
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M1_n => M1_n,
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MREQ_n => MREQ_n_int,
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IORQ_n => IORQ_n_int,
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RD_n => RD_n_int,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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BUSAK_n => BUSAK_n,
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Addr => Addr_int,
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Data => Data,
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-- Buffer Control Signals
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tristate_n => tristate_n,
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DIRD => open,
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-- Mode jumper, tie low to generate NOPs when paused
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mode => mode,
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-- External trigger inputs
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trig => trig,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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2019-11-04 09:31:56 +00:00
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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2019-11-02 13:26:00 +00:00
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-- LEDs
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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-- OHO_DY1 connected to test connector
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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-- Debugging signals
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test1 => test1,
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test2 => test2,
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test3 => test3,
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test4 => test4
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);
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end behavioral;
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