diff --git a/src/MOS6502CpuMon.vhd b/src/MOS6502CpuMon.vhd index e4f3576..337aea7 100644 --- a/src/MOS6502CpuMon.vhd +++ b/src/MOS6502CpuMon.vhd @@ -48,14 +48,14 @@ entity MOS6502CpuMon is Rdy : in std_logic; -- External trigger inputs - trig : in std_logic_vector(1 downto 0); + trig : in std_logic_vector(1 downto 0); -- Jumpers - fakeTube_n : in std_logic; + fakeTube_n : in std_logic; -- Serial Console - avr_RxD : in std_logic; - avr_TxD : out std_logic; + avr_RxD : in std_logic; + avr_TxD : out std_logic; -- Switches sw_reset_cpu : in std_logic; @@ -67,9 +67,12 @@ entity MOS6502CpuMon is led_trig1 : out std_logic; -- OHO_DY1 connected to test connector - tmosi : out std_logic; - tdin : out std_logic; - tcclk : out std_logic + tmosi : out std_logic; + tdin : out std_logic; + tcclk : out std_logic; + + -- Test connector signals + test : inout std_logic_vector(3 downto 0) ); end MOS6502CpuMon; @@ -141,7 +144,8 @@ begin led_trig1 => led_trig1, tmosi => tmosi, tdin => tdin, - tcclk => tcclk + tcclk => tcclk, + test => test ); sync_gen : process(cpu_clk) diff --git a/src/MOS6502CpuMonALS.vhd b/src/MOS6502CpuMonALS.vhd index 10208bb..69c006c 100644 --- a/src/MOS6502CpuMonALS.vhd +++ b/src/MOS6502CpuMonALS.vhd @@ -79,18 +79,21 @@ entity MOS6502CpuMonALS is avr_TxD : out std_logic; -- Switches - sw1 : in std_logic; - sw2 : in std_logic; + sw1 : in std_logic; + sw2 : in std_logic; -- LEDs - led1 : out std_logic; - led2 : out std_logic; - led3 : out std_logic; + led1 : out std_logic; + led2 : out std_logic; + led3 : out std_logic; -- OHO_DY1 LED display - tmosi : out std_logic; - tdin : out std_logic; - tcclk : out std_logic + tmosi : out std_logic; + tdin : out std_logic; + tcclk : out std_logic; + + -- Test connector signals + test : inout std_logic_vector(3 downto 0) ); end MOS6502CpuMonALS; @@ -166,7 +169,10 @@ begin -- OHO_DY1 LED display tmosi => tmosi, tdin => tdin, - tcclk => tcclk + tcclk => tcclk, + + -- Test signals + test => test ); -- 6502 Outputs diff --git a/src/MOS6502CpuMonCore.vhd b/src/MOS6502CpuMonCore.vhd index a9772e3..030fd58 100644 --- a/src/MOS6502CpuMonCore.vhd +++ b/src/MOS6502CpuMonCore.vhd @@ -67,7 +67,10 @@ entity MOS6502CpuMonCore is -- OHO_DY1 connected to test connector tmosi : out std_logic; tdin : out std_logic; - tcclk : out std_logic + tcclk : out std_logic; + + -- Test connector signals + test : inout std_logic_vector(3 downto 0) ); end MOS6502CpuMonCore; @@ -391,4 +394,10 @@ begin memory_din <= Din; + -- Test outputs + test(0) <= SS_Single; -- GODIL J5 pin 1 (46) + test(1) <= 'Z'; -- GODIL J5 pin 2 (47) + test(2) <= 'Z'; -- GODIL J5 pin 3 (48) + test(3) <= 'Z'; -- GODIL J5 pin 4 (56) + end behavioral; diff --git a/target/lx9_dave/ice6502/board.ucf b/target/lx9_dave/ice6502/board.ucf index d904d8c..f4d95c2 100644 --- a/target/lx9_dave/ice6502/board.ucf +++ b/target/lx9_dave/ice6502/board.ucf @@ -88,7 +88,7 @@ NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Test outputs (connect to J5 on FPGA board) -#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<0>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<1>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<3>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; diff --git a/target/lx9_dave/ice65c02/board.ucf b/target/lx9_dave/ice65c02/board.ucf index d904d8c..f4d95c2 100644 --- a/target/lx9_dave/ice65c02/board.ucf +++ b/target/lx9_dave/ice65c02/board.ucf @@ -88,7 +88,7 @@ NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Test outputs (connect to J5 on FPGA board) -#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<0>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<1>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test<3>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;