From 08cfc81ba101867498ebd4df5fb576bef655b825 Mon Sep 17 00:00:00 2001 From: David Banks Date: Mon, 4 Nov 2019 15:21:57 +0000 Subject: [PATCH] GODIL: Tidy up .ucf files, all pins 8ms drive Change-Id: I77d82e3249993deb52151df13229850f63ebc15b --- target/godil_250/_icez80/board.ucf | 53 +++++------- target/godil_250/ice6502/board.ucf | 116 +++++++++++++------------- target/godil_250/ice65c02/board.ucf | 116 +++++++++++++------------- target/godil_250/ice6809/board.ucf | 122 +++++++++++++--------------- target/godil_500/ice6502/board.ucf | 116 +++++++++++++------------- target/godil_500/ice65c02/board.ucf | 116 +++++++++++++------------- target/godil_500/ice6809/board.ucf | 122 +++++++++++++--------------- target/godil_500/icez80/board.ucf | 53 +++++------- 8 files changed, 386 insertions(+), 428 deletions(-) diff --git a/target/godil_250/_icez80/board.ucf b/target/godil_250/_icez80/board.ucf index f084627..73728d7 100644 --- a/target/godil_250/_icez80/board.ucf +++ b/target/godil_250/_icez80/board.ucf @@ -1,6 +1,5 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE; -TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW; NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; @@ -11,7 +10,7 @@ NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3 NET "Addr<14>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 4 NET "Addr<15>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 5 -NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # Z80 pin 6 +NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PERIOD = 125.00ns ; # Z80 pin 6 NET "Data<4>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 7 NET "Data<3>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 8 NET "Data<5>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 9 @@ -47,39 +46,31 @@ NET "Addr<8>" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z NET "Addr<9>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 39 NET "Addr<10>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Left Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Right Switch # I/O's for test connector -#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # This input controls whether the idle mode includes M1 cycles -NET "mode" LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP; - -# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +NET "mode" LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP; diff --git a/target/godil_250/ice6502/board.ucf b/target/godil_250/ice6502/board.ucf index 243e6cf..49d0cd1 100644 --- a/target/godil_250/ice6502/board.ucf +++ b/target/godil_250/ice6502/board.ucf @@ -4,68 +4,68 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH; NET "Phi0" TNM_NET = clk_period_grp_phi0; TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW; -NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator -#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 -NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 -NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3 -NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 -#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 -NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 -NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7 -#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 -NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9 -NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10 -NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11 -NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12 -NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13 -NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14 -NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15 -NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16 -NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17 -NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18 -NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19 -NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20 +NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator +#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 +NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 +NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3 +NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 +#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 +NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 +NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7 +#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 +NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9 +NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10 +NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11 +NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12 +NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13 +NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14 +NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15 +NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16 +NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17 +NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18 +NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19 +NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20 -#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 -NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22 -NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23 -NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24 -NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25 -NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26 -NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27 -NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28 -NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29 -NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30 -NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31 -NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32 -NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33 -NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34 -#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 -#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 -NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 -NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 -NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39 -NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 +#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 +NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22 +NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23 +NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24 +NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25 +NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26 +NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27 +NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28 +NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29 +NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30 +NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31 +NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32 +NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33 +NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34 +#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 +#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 +NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 +NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 +NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39 +NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch # I/O's for test connector -#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; +NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; diff --git a/target/godil_250/ice65c02/board.ucf b/target/godil_250/ice65c02/board.ucf index 243e6cf..49d0cd1 100644 --- a/target/godil_250/ice65c02/board.ucf +++ b/target/godil_250/ice65c02/board.ucf @@ -4,68 +4,68 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH; NET "Phi0" TNM_NET = clk_period_grp_phi0; TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW; -NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator -#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 -NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 -NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3 -NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 -#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 -NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 -NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7 -#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 -NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9 -NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10 -NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11 -NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12 -NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13 -NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14 -NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15 -NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16 -NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17 -NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18 -NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19 -NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20 +NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator +#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 +NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 +NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3 +NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 +#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 +NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 +NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7 +#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 +NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9 +NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10 +NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11 +NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12 +NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13 +NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14 +NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15 +NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16 +NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17 +NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18 +NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19 +NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20 -#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 -NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22 -NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23 -NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24 -NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25 -NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26 -NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27 -NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28 -NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29 -NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30 -NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31 -NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32 -NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33 -NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34 -#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 -#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 -NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 -NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 -NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39 -NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 +#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 +NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22 +NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23 +NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24 +NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25 +NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26 +NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27 +NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28 +NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29 +NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30 +NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31 +NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32 +NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33 +NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34 +#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 +#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 +NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 +NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 +NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39 +NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch # I/O's for test connector -#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; +NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; diff --git a/target/godil_250/ice6809/board.ucf b/target/godil_250/ice6809/board.ucf index 71af61e..cdcc00d 100644 --- a/target/godil_250/ice6809/board.ucf +++ b/target/godil_250/ice6809/board.ucf @@ -1,5 +1,5 @@ NET "E" CLOCK_DEDICATED_ROUTE = FALSE; -NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; +NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator @@ -7,83 +7,71 @@ NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.15 NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2 NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3 NET "FIRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6809 pin 4 -NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 5 -NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 6 +NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 5 +NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 6 #NET "VCC" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6809 pin 7 -NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 8 -NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 9 -NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 10 -NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 11 -NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 12 -NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 13 -NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 14 -NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 15 -NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 16 -NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 17 -NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 18 -NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 19 -NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 20 -NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 21 -NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 22 -NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 23 -NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 24 -NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 25 -NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 26 -NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 27 -NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 28 -NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 29 -NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 30 -NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 31 -NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 32 -NET "PIN33" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 33 -NET "PIN34" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 34 -NET "PIN35" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 35 -NET "PIN36" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 36 +NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 8 +NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 9 +NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 10 +NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 11 +NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 12 +NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 13 +NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 14 +NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 15 +NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 16 +NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 17 +NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 18 +NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 19 +NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 20 +NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 21 +NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 22 +NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 23 +NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 24 +NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 25 +NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 26 +NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 27 +NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 28 +NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 29 +NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 30 +NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 31 +NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 32 +NET "PIN33" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 33 +NET "PIN34" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 34 +NET "PIN35" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 35 +NET "PIN36" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 36 NET "RES_n" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6809 pin 37 -NET "PIN38" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 38 +NET "PIN38" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 38 NET "PIN39" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6809 pin 39 NET "HALT_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6809 pin 40 # A jumper to enable 6809E mode NET "EMode_n" LOC="P91" | IOSTANDARD = LVCMOS33 ; -# A clock generated from the GODIL's 49.152MHz clock -NET "clock_test" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; +# A clock generated from the GODIL's 49.152MHz clock +NET "clock_test" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Left Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Right Switch # I/O's for test connector -#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -# NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -# NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; - - -# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 - - - \ No newline at end of file +NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; diff --git a/target/godil_500/ice6502/board.ucf b/target/godil_500/ice6502/board.ucf index 243e6cf..49d0cd1 100644 --- a/target/godil_500/ice6502/board.ucf +++ b/target/godil_500/ice6502/board.ucf @@ -4,68 +4,68 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH; NET "Phi0" TNM_NET = clk_period_grp_phi0; TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW; -NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator -#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 -NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 -NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3 -NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 -#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 -NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 -NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7 -#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 -NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9 -NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10 -NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11 -NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12 -NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13 -NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14 -NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15 -NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16 -NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17 -NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18 -NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19 -NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20 +NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator +#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 +NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 +NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3 +NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 +#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 +NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 +NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7 +#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 +NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9 +NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10 +NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11 +NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12 +NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13 +NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14 +NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15 +NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16 +NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17 +NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18 +NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19 +NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20 -#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 -NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22 -NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23 -NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24 -NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25 -NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26 -NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27 -NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28 -NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29 -NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30 -NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31 -NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32 -NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33 -NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34 -#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 -#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 -NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 -NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 -NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39 -NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 +#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 +NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22 +NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23 +NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24 +NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25 +NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26 +NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27 +NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28 +NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29 +NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30 +NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31 +NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32 +NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33 +NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34 +#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 +#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 +NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 +NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 +NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39 +NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch # I/O's for test connector -#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; +NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; diff --git a/target/godil_500/ice65c02/board.ucf b/target/godil_500/ice65c02/board.ucf index 243e6cf..49d0cd1 100644 --- a/target/godil_500/ice65c02/board.ucf +++ b/target/godil_500/ice65c02/board.ucf @@ -4,68 +4,68 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH; NET "Phi0" TNM_NET = clk_period_grp_phi0; TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW; -NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator -#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 -NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 -NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3 -NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 -#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 -NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 -NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7 -#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 -NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9 -NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10 -NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11 -NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12 -NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13 -NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14 -NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15 -NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16 -NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17 -NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18 -NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19 -NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20 +NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator +#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1 +NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2 +NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3 +NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4 +#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5 +NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6 +NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7 +#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8 +NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9 +NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10 +NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11 +NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12 +NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13 +NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14 +NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15 +NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16 +NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17 +NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18 +NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19 +NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20 -#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 -NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22 -NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23 -NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24 -NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25 -NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26 -NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27 -NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28 -NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29 -NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30 -NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31 -NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32 -NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33 -NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34 -#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 -#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 -NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 -NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 -NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39 -NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 +#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21 +NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22 +NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23 +NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24 +NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25 +NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26 +NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27 +NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28 +NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29 +NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30 +NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31 +NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32 +NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33 +NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34 +#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35 +#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36 +NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37 +NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38 +NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39 +NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch # I/O's for test connector -#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; +NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ; diff --git a/target/godil_500/ice6809/board.ucf b/target/godil_500/ice6809/board.ucf index 71af61e..cdcc00d 100644 --- a/target/godil_500/ice6809/board.ucf +++ b/target/godil_500/ice6809/board.ucf @@ -1,5 +1,5 @@ NET "E" CLOCK_DEDICATED_ROUTE = FALSE; -NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; +NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator @@ -7,83 +7,71 @@ NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.15 NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2 NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3 NET "FIRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6809 pin 4 -NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 5 -NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 6 +NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 5 +NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 6 #NET "VCC" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6809 pin 7 -NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 8 -NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 9 -NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 10 -NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 11 -NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 12 -NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 13 -NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 14 -NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 15 -NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 16 -NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 17 -NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 18 -NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 19 -NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 20 -NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 21 -NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 22 -NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 23 -NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 24 -NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 25 -NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 26 -NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 27 -NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 28 -NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 29 -NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 30 -NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 31 -NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 32 -NET "PIN33" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 33 -NET "PIN34" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 34 -NET "PIN35" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 35 -NET "PIN36" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 36 +NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 8 +NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 9 +NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 10 +NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 11 +NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 12 +NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 13 +NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 14 +NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 15 +NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 16 +NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 17 +NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 18 +NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 19 +NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 20 +NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 21 +NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 22 +NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 23 +NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 24 +NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 25 +NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 26 +NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 27 +NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 28 +NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 29 +NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 30 +NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 31 +NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 32 +NET "PIN33" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 33 +NET "PIN34" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 34 +NET "PIN35" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 35 +NET "PIN36" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 36 NET "RES_n" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6809 pin 37 -NET "PIN38" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 38 +NET "PIN38" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6809 pin 38 NET "PIN39" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6809 pin 39 NET "HALT_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6809 pin 40 # A jumper to enable 6809E mode NET "EMode_n" LOC="P91" | IOSTANDARD = LVCMOS33 ; -# A clock generated from the GODIL's 49.152MHz clock -NET "clock_test" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; +# A clock generated from the GODIL's 49.152MHz clock +NET "clock_test" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Left Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Right Switch # I/O's for test connector -#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -# NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -# NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; - - -# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 - - - \ No newline at end of file +NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; diff --git a/target/godil_500/icez80/board.ucf b/target/godil_500/icez80/board.ucf index f084627..73728d7 100644 --- a/target/godil_500/icez80/board.ucf +++ b/target/godil_500/icez80/board.ucf @@ -1,6 +1,5 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE; -TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW; NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE; @@ -11,7 +10,7 @@ NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3 NET "Addr<14>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 4 NET "Addr<15>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 5 -NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # Z80 pin 6 +NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PERIOD = 125.00ns ; # Z80 pin 6 NET "Data<4>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 7 NET "Data<3>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 8 NET "Data<5>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 9 @@ -47,39 +46,31 @@ NET "Addr<8>" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z NET "Addr<9>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 39 NET "Addr<10>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 40 -NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) -NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) -NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) -NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch -NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch +NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1) +NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) +NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) +NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Left Switch +NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Right Switch # I/O's for test connector -#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; -#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2 +#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3 +NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4 +NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5 +NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6 +#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7 +#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8 -NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; -NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; +NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ; +NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ; -NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ; -NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # This input controls whether the idle mode includes M1 cycles -NET "mode" LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP; - -# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 -# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3 -# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4 -# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5 -# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6 -# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7 -# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8 +NET "mode" LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP;