diff --git a/src/W65C02CpuMon.vhd b/src/W65C02CpuMon.vhd
new file mode 100644
index 0000000..23319eb
--- /dev/null
+++ b/src/W65C02CpuMon.vhd
@@ -0,0 +1,168 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2018 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : W65C02CpuMon.vhd
+-- /___/   /\     Timestamp : 20/11/2018
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: W65C02BusMon
+--Device: XC6SLX9
+--
+--
+-- This is a small wrapper around AtomCpuMon that add the following signals:
+--   OEAH_n
+--   OEAL_n
+--   OED_n
+--   BE
+--   ML_n
+--   VP_n
+-- (these are not fully implemented yet)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity W65C02CpuMon is
+    generic (
+       UseT65Core     : boolean := true;
+       UseAlanDCore   : boolean := false;
+       LEDsActiveHigh : boolean := true;     -- default value for EEPIZZA
+       SW1ActiveHigh  : boolean := true;     -- default value for EEPIZZA
+       SW2ActiveHigh  : boolean := true;     -- default value for EEPIZZA
+       ClkMult        : integer := 10;       -- default value for EEPIZZA
+       ClkDiv         : integer := 31;       -- default value for EEPIZZA
+       ClkPer         : real    := 20.000    -- default value for EEPIZZA
+       );
+    port (
+        clock49         : in    std_logic;
+
+        -- 6502 Signals
+        Phi0            : in    std_logic;
+        Phi1            : out   std_logic;
+        Phi2            : out   std_logic;
+        IRQ_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        Sync            : out   std_logic;
+        Addr            : out   std_logic_vector(15 downto 0);
+        R_W_n           : out   std_logic;
+        Data            : inout std_logic_vector(7 downto 0);
+        SO_n            : in    std_logic;
+        Res_n           : inout std_logic;
+        Rdy             : in    std_logic;
+
+        -- 65C02 Signals
+        BE              : in    std_logic;
+        ML_n            : out   std_logic;
+        VP_n            : out   std_logic;
+
+        -- Level Shifter Controls
+        OEAH_n          : out   std_logic;
+        OEAL_n          : out   std_logic;
+        OED_n           : out   std_logic;
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Jumpers
+        fakeTube_n      : in    std_logic;
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- Switches
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
+
+        -- LEDs
+        led3             : out  std_logic;
+        led6             : out  std_logic;
+        led8             : out  std_logic;
+
+        -- OHO_DY1 LED display
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic
+    );
+end W65C02CpuMon;
+
+architecture behavioral of W65C02CpuMon is
+
+    signal R_W_n_int     : std_logic;
+
+begin
+
+    acm : entity work.AtomCpuMon
+    generic map (
+       UseT65Core     => UseT65Core,
+       UseAlanDCore   => UseAlanDCore,
+       LEDsActiveHigh => LEDsActiveHigh,
+       SW1ActiveHigh  => SW1ActiveHigh,
+       SW2ActiveHigh  => SW2ActiveHigh,
+       ClkMult        => ClkMult,
+       ClkDiv         => ClkDiv,
+       ClkPer         => ClkPer
+    )
+    port map (
+        clock49         => clock49,
+
+        -- 6502 Signals
+        Phi0            => Phi0,
+        Phi1            => Phi1,
+        Phi2            => Phi2,
+        IRQ_n           => IRQ_n,
+        NMI_n           => NMI_n,
+        Sync            => Sync,
+        Addr            => Addr,
+        R_W_n           => R_W_n_int,
+        Data            => Data,
+        SO_n            => SO_n,
+        Res_n           => Res_n,
+        Rdy             => Rdy,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Jumpers
+        fakeTube_n      => fakeTube_n,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw1              => sw1,
+        sw2              => sw2,
+
+        -- LEDs
+        led3             => led3,
+        led6             => led6,
+        led8             => led8,
+
+        -- OHO_DY1 LED display
+        tmosi            => tmosi,
+        tdin             => tdin,
+        tcclk            => tcclk
+    );
+
+    -- 6502 Outputs
+    R_W_n <= R_W_n_int;
+
+    -- 65C02 Outputs
+    ML_n   <= '1';
+    VP_n   <= '1';
+
+    -- Level Shifter Controls
+    OEAH_n <= not (BE);
+    OEAL_n <= not (BE);
+    OED_n  <= not (BE or (Phi0 and not R_W_n_int)); -- TODO: might need to use a slightly delayed version of Phi0 here
+
+end behavioral;
diff --git a/target/lx9_dave/ice6502/Makefile b/target/lx9_dave/ice6502/Makefile
index 218d489..f3a0725 100644
--- a/target/lx9_dave/ice6502/Makefile
+++ b/target/lx9_dave/ice6502/Makefile
@@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = AtomCpuMon
+PROJECT    = W65C02CpuMon
 
 # The target .bit file to be generated including the monitor program
 TARGET     = ice6502
diff --git a/target/lx9_dave/ice6502/board.ucf b/target/lx9_dave/ice6502/board.ucf
index 31359a3..0516563 100644
--- a/target/lx9_dave/ice6502/board.ucf
+++ b/target/lx9_dave/ice6502/board.ucf
@@ -6,73 +6,77 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW;
 
 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "clock49"  LOC="P21"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+NET "clock49"  LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
-#NET "VSS"     LOC="P"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
-#NET "Rdy"     LOC="P"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
-NET "Phi1"     LOC="P30"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
-NET "IRQ_n"    LOC="P32"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
-#NET "NC"      LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
-NET "NMI_n"    LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
-NET "Sync"     LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
-#NET "VCC"     LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
-NET "Addr<0>"  LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
-NET "Addr<1>"  LOC="P41"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
-NET "Addr<2>"  LOC="P43"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
-NET "Addr<3>"  LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
-NET "Addr<4>"  LOC="P50"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
-NET "Addr<5>"  LOC="P51"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
-NET "Addr<6>"  LOC="P55"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
-NET "Addr<7>"  LOC="P56"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
-NET "Addr<8>"  LOC="P62"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
-NET "Addr<9>"  LOC="P66"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
-NET "Addr<10>" LOC="P67"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
-NET "Addr<11>" LOC="P74"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
+NET "VP_n"     LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
+#NET "Rdy"     LOC="P79"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
+NET "Phi1"     LOC="P33"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
+NET "IRQ_n"    LOC="P81"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
+NET "ML_n"     LOC="P34"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
+NET "NMI_n"    LOC="P82"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
+NET "Sync"     LOC="P32"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
+#NET "VCC"     LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
+NET "Addr<0>"  LOC="P22"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
+NET "Addr<1>"  LOC="P23"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
+NET "Addr<2>"  LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
+NET "Addr<3>"  LOC="P21"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
+NET "Addr<4>"  LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
+NET "Addr<5>"  LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
+NET "Addr<6>"  LOC="P12"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
+NET "Addr<7>"  LOC="P14"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
+NET "Addr<8>"  LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
+NET "Addr<9>"  LOC="P1"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
+NET "Addr<10>" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
+NET "Addr<11>" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
 
-#NET "VSS"     LOC="P"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
-NET "Addr<12>" LOC="P78"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
-NET "Addr<13>" LOC="P79"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
-NET "Addr<14>" LOC="P80"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
-NET "Addr<15>" LOC="P81"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
-NET "Data<7>"  LOC="P82"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
-NET "Data<6>"  LOC="P83"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
-NET "Data<5>"  LOC="P84"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
-NET "Data<4>"  LOC="P75"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
-NET "Data<3>"  LOC="P85"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
-NET "Data<2>"  LOC="P87"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
-NET "Data<1>"  LOC="P88"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
-NET "Data<0>"  LOC="P92"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
-NET "R_W_n"    LOC="P93"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
-#NET "NC"      LOC="P94"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
-#NET "NC"      LOC="P95"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
-NET "Phi0"     LOC="P97"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
-NET "SO_n"     LOC="P98"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
-NET "Phi2"     LOC="P99"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
-NET "Res_n"    LOC="P100"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
+#NET "VSS"     LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
+NET "Addr<12>" LOC="P5"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
+NET "Addr<13>" LOC="P2"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
+NET "Addr<14>" LOC="P7"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
+NET "Addr<15>" LOC="P6"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
+NET "Data<7>"  LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
+NET "Data<6>"  LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
+NET "Data<5>"  LOC="P99"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
+NET "Data<4>"  LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
+NET "Data<3>"  LOC="P97"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
+NET "Data<2>"  LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
+NET "Data<1>"  LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
+NET "Data<0>"  LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
+NET "R_W_n"    LOC="P30"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
+#NET "NC"      LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
+NET "BE"       LOC="P83"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
+NET "Phi0"     LOC="P40"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
+NET "SO_n"     LOC="P78"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
+NET "Phi2"     LOC="P80"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
+NET "Res_n"    LOC="P74"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
 
+# Level-shifter OE signals
+NET "OEAL_n"   LOC="P10"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OEAH_n"   LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OED_n"    LOC="P92"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # LEDs and Switches
-NET "led3"     LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
-NET "led6"     LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
-NET "led8"     LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
-NET "sw1"      LOC="P133" | IOSTANDARD = LVCMOS33                           ; # reset
-NET "sw2"      LOC="P132" | IOSTANDARD = LVCMOS33                           ; # interrupt
+NET "led3"     LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
+NET "led6"     LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
+NET "led8"     LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
+NET "sw1"      LOC="P132" | IOSTANDARD = LVCMOS33                           ; # reset
+NET "sw2"      LOC="P131" | IOSTANDARD = LVCMOS33                           ; # interrupt
 
 # 7-segment LED
-NET tmosi      LOC="P101"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-NET tdin       LOC="P102"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-NET tcclk      LOC="P104"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET tmosi      LOC="P45"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET tdin       LOC="P44"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET tcclk      LOC="P43"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # UART
-NET "avr_TxD"  LOC="P22"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-NET "avr_RxD"  LOC="P23"  | IOSTANDARD = LVCMOS33                           ;
+NET "avr_TxD"  LOC="P51"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "avr_RxD"  LOC="P55"  | IOSTANDARD = LVCMOS33                           ;
 
 # External trigger inputs
-NET "trig<0>"  LOC="P134" | IOSTANDARD = LVCMOS33                           ;
-NET "trig<1>"  LOC="P137" | IOSTANDARD = LVCMOS33                           ;
+NET "trig<0>"  LOC="P126" | IOSTANDARD = LVCMOS33                           ;
+NET "trig<1>"  LOC="P127" | IOSTANDARD = LVCMOS33                           ;
 
 # Jumpers
-NET "fakeTube_n" LOC="P27" | IOSTANDARD = LVCMOS33 ;
+NET "fakeTube_n" LOC="P123" | IOSTANDARD = LVCMOS33                         ;
 
 
 
diff --git a/target/lx9_dave/ice6502/ice6502.xise b/target/lx9_dave/ice6502/ice6502.xise
index a6008b7..5bda8d7 100644
--- a/target/lx9_dave/ice6502/ice6502.xise
+++ b/target/lx9_dave/ice6502/ice6502.xise
@@ -257,6 +257,10 @@
     <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../../src/W65C02CpuMon.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+    </file>
     <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -380,9 +384,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|W65C02CpuMon|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/W65C02CpuMon.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/W65C02CpuMon" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -451,7 +455,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -466,10 +470,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="W65C02CpuMon_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="W65C02CpuMon_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="W65C02CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="W65C02CpuMon_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -493,7 +497,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
diff --git a/target/lx9_dave/ice6502/memory.bmm b/target/lx9_dave/ice6502/memory.bmm
index 7acc1c1..4a652c5 100644
--- a/target/lx9_dave/ice6502/memory.bmm
+++ b/target/lx9_dave/ice6502/memory.bmm
@@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
 
     ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+            acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
         END_BUS_BLOCK;
 
     END_ADDRESS_SPACE;