Z80: seperate top level for GODIL and old LX9

Change-Id: I1f339996037bb8a20afb7664877e0ed1d53d3868

src/Z80CpuMonALS.vhd

@@ -22,9 +22,6 @@ use ieee.numeric_std.all;
 
 entity Z80CpuMonALS is
     generic (
-        Clkmult           : integer := 8;        -- default value for lx9core board
-        ClkDiv            : integer := 25;       -- default value for lx9core board
-        ClkPer            : real    := 20.000;   -- default value for lx9core board
         num_comparators   : integer := 8;        -- default value for lx9core board
         avr_prog_mem_size : integer := 1024 * 16 -- default value for lx9core board
         );
@@ -89,18 +86,30 @@ end Z80CpuMonALS;
 
 architecture behavioral of Z80CpuMonALS is
 
-    signal MREQ_n_int  : std_logic;
+    signal MREQ_n_int   : std_logic;
-    signal IORQ_n_int  : std_logic;
+    signal IORQ_n_int   : std_logic;
-    signal M1_n_int    : std_logic;
+    signal M1_n_int     : std_logic;
-    signal RD_n_int    : std_logic;
+    signal RD_n_int     : std_logic;
-    signal WR_n_int    : std_logic;
+    signal WR_n_int     : std_logic;
-    signal RFSH_n_int  : std_logic;
+    signal RFSH_n_int   : std_logic;
-    signal HALT_n_int  : std_logic;
+    signal HALT_n_int   : std_logic;
-    signal BUSAK_n_int : std_logic;
+    signal BUSAK_n_int  : std_logic;
-    signal tristate_n  : std_logic;
+    signal tristate_n   : std_logic;
+
+    signal sw_interrupt : std_logic;
+    signal sw_reset     : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
 
 begin
 
+    sw_interrupt <= not sw1;
+    sw_reset     <= not sw2;
+    led1         <= led_bkpt;
+    led2         <= led_trig0;
+    led3         <= led_trig1;
+
     MREQ_n  <= MREQ_n_int;
     IORQ_n  <= IORQ_n_int;
     M1_n    <= M1_n_int;
@@ -120,8 +129,8 @@ begin
             ClkMult           => 8,
             ClkDiv            => 25,
             ClkPer            => 20.000,
-            num_comparators   => 8,
+            num_comparators   => num_comparators,
-            avr_prog_mem_size => 1024 * 16
+            avr_prog_mem_size => avr_prog_mem_size
             )
         port map (
             clock49           => clock,
@@ -159,13 +168,13 @@ begin
             avr_TxD           => avr_TxD,
 
             -- Switches
-            sw_interrupt      => not sw1,
+            sw_interrupt      => sw_interrupt,
-            sw_reset          => not sw2,
+            sw_reset          => sw_reset,
 
             -- LEDs
-            led_bkpt          => led1,
+            led_bkpt          => led_bkpt,
-            led_trig0         => led2,
+            led_trig0         => led_trig0,
-            led_trig1         => led3,
+            led_trig1         => led_trig1,
 
             -- OHO_DY1 connected to test connector
             tmosi             => tmosi,

src/Z80CpuMonGODIL.vhd

@@ -13,7 +13,7 @@
 --  \___\/\___\
 --
 --Design Name: Z80CpuMonGODIL
---Device: multiple
+--Device: XC3S500E
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -22,12 +22,6 @@ use ieee.numeric_std.all;
 
 entity Z80CpuMonGODIL is
     generic (
-        LEDsActiveHigh    : boolean := false;    -- default value correct for GODIL
-        SW1ActiveHigh     : boolean := true;     -- default value correct for GODIL
-        SW2ActiveHigh     : boolean := false;    -- default value correct for GODIL
-        ClkMult           : integer := 10;       -- default value correct for GODIL
-        ClkDiv            : integer := 31;       -- default value correct for GODIL
-        ClkPer            : real    := 20.345;   -- default value correct for GODIL
         num_comparators   : integer := 8;        -- default value correct for GODIL
         avr_prog_mem_size : integer := 1024 * 16 -- default value correct for GODIL
         );
@@ -102,12 +96,11 @@ architecture behavioral of Z80CpuMonGODIL is
     signal tristate_n   : std_logic;
 
 begin
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
+    sw_interrupt <= sw1;
-    sw_interrupt <= sw1       when SW1ActiveHigh  else not sw1;
+    sw_reset     <= not sw2;
-    sw_reset     <= sw2       when SW2ActiveHigh  else not sw2;
+    led3         <= not led_trig0;
-    led3         <= led_trig0 when LEDsActiveHigh else not led_trig0;
+    led6         <= not led_trig1;
-    led6         <= led_trig1 when LEDsActiveHigh else not led_trig1;
+    led8         <= not led_bkpt;
-    led8         <= led_bkpt  when LEDsActiveHigh else not led_bkpt;
 
     -- Tristateable output drivers
     MREQ_n <= 'Z'             when tristate_n = '0' else MREQ_n_int;
@@ -118,9 +111,9 @@ begin
 
     wrapper : entity work.Z80CpuMon
         generic map (
-            ClkMult           => ClkMult,
+            ClkMult           => 10,
-            ClkDiv            => ClkDiv,
+            ClkDiv            => 31,
-            ClkPer            => ClkPer,
+            ClkPer            => 20.345,
             num_comparators   => num_comparators,
             avr_prog_mem_size => avr_prog_mem_size
             )

src/Z80CpuMonLX9.vhd

@@ -0,0 +1,177 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : Z80CpuMonLX9.vhd
+-- /___/   /\     Timestamp : 14/10/2018
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: Z80CpuMonLX9
+--Device: XC6SLX9
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity Z80CpuMonLX9 is
+    generic (
+        num_comparators   : integer := 8;        -- default value correct for LX9
+        avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
+        );
+    port (
+        clock49         : in    std_logic;
+
+        -- Z80 Signals
+        RESET_n         : in    std_logic;
+        CLK_n           : in    std_logic;
+        WAIT_n          : in    std_logic;
+        INT_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        BUSRQ_n         : in    std_logic;
+        M1_n            : out   std_logic;
+        MREQ_n          : out   std_logic;
+        IORQ_n          : out   std_logic;
+        RD_n            : out   std_logic;
+        WR_n            : out   std_logic;
+        RFSH_n          : out   std_logic;
+        HALT_n          : out   std_logic;
+        BUSAK_n         : out   std_logic;
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- Mode jumper, tie low to generate NOPs when paused
+        mode            : in    std_logic;
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- LX9 Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- LX9 LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic;
+        test3           : out   std_logic;
+        test4           : out   std_logic
+
+        );
+end Z80CpuMonLX9;
+
+architecture behavioral of Z80CpuMonLX9 is
+
+    signal sw_reset     : std_logic;
+    signal sw_interrupt : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+    signal MREQ_n_int   : std_logic;
+    signal IORQ_n_int   : std_logic;
+    signal RD_n_int     : std_logic;
+    signal WR_n_int     : std_logic;
+    signal Addr_int     : std_logic_vector(15 downto 0);
+
+    signal tristate_n   : std_logic;
+
+begin
+
+    sw_interrupt <= sw1;
+    sw_reset     <= sw2;
+    led3         <= led_trig0;
+    led6         <= led_trig1;
+    led8         <= led_bkpt;
+
+    -- Tristateable output drivers
+    MREQ_n <= 'Z'             when tristate_n = '0' else MREQ_n_int;
+    IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
+    RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
+    WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
+    Addr   <= (others => 'Z') when tristate_n = '0' else Addr_int;
+
+    wrapper : entity work.Z80CpuMon
+        generic map (
+            ClkMult           => 8,
+            ClkDiv            => 25,
+            ClkPer            => 20.000,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map(
+            clock49         =>  clock49,
+
+            -- Z80 Signals
+            RESET_n         =>  RESET_n,
+            CLK_n           =>  CLK_n,
+            WAIT_n          =>  WAIT_n,
+            INT_n           =>  INT_n,
+            NMI_n           =>  NMI_n,
+            BUSRQ_n         =>  BUSRQ_n,
+            M1_n            =>  M1_n,
+            MREQ_n          =>  MREQ_n_int,
+            IORQ_n          =>  IORQ_n_int,
+            RD_n            =>  RD_n_int,
+            WR_n            =>  WR_n_int,
+            RFSH_n          =>  RFSH_n,
+            HALT_n          =>  HALT_n,
+            BUSAK_n         =>  BUSAK_n,
+            Addr            =>  Addr_int,
+            Data            =>  Data,
+
+            -- Buffer Control Signals
+            tristate_n      =>  tristate_n,
+            DIRD            =>  open,
+
+            -- Mode jumper, tie low to generate NOPs when paused
+            mode            =>  mode,
+
+            -- External trigger inputs
+            trig            =>  trig,
+
+            -- Serial Console
+            avr_RxD         =>  avr_RxD,
+            avr_TxD         =>  avr_TxD,
+
+            -- Switches
+            sw_interrupt    => sw_interrupt,
+            sw_reset        => sw_reset,
+
+            -- LEDs
+            led_bkpt        => led_bkpt,
+            led_trig0       => led_trig0,
+            led_trig1       => led_trig1,
+
+            -- OHO_DY1 connected to test connector
+            tmosi           =>  tmosi,
+            tdin            =>  tdin,
+            tcclk           =>  tcclk,
+
+            -- Debugging signals
+            test1           =>  test1,
+            test2           =>  test2,
+            test3           =>  test3,
+            test4           =>  test4
+            );
+
+end behavioral;

target/lx9_jason/icez80/Makefile

@@ -5,13 +5,13 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = Z80CpuMonGODIL
+PROJECT    = Z80CpuMonLX9
 
 # The target .bit file to be generated including the monitor program
 TARGET     = icez80
 
 # Frequuency that the AVR runs at
-F_CPU      = 19354838
+F_CPU      = 16000000
 
 # Common include files
 include $(COMMON)/Makefile_$(TARGET).inc

target/lx9_jason/icez80/icez80.xise

@@ -257,7 +257,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
     </file>
-    <file xil_pn:name="../../../src/Z80CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/Z80CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
     </file>
@@ -374,7 +374,7 @@
     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@@ -383,9 +383,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMonLX9|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMonLX9.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMonGODIL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMonLX9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -454,7 +454,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMonLX9" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -469,10 +469,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMonLX9_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMonLX9_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMonLX9_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMonLX9_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -496,7 +496,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMonLX9" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

target/lx9_jason_flipped/icez80/Makefile

@@ -5,13 +5,13 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = Z80CpuMonGODIL
+PROJECT    = Z80CpuMonLX9
 
 # The target .bit file to be generated including the monitor program
 TARGET     = icez80
 
 # Frequuency that the AVR runs at
-F_CPU      = 19354838
+F_CPU      = 16000000
 
 # Common include files
 include $(COMMON)/Makefile_$(TARGET).inc

target/lx9_jason_flipped/icez80/icez80.xise

@@ -257,7 +257,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
     </file>
-    <file xil_pn:name="../../../src/Z80CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/Z80CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
     </file>
@@ -374,7 +374,7 @@
     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@@ -383,9 +383,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMonLX9|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMonLX9.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMonGODIL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMonLX9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -454,7 +454,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMonLX9" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -469,10 +469,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMonLX9_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMonLX9_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMonLX9_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMonLX9_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -496,7 +496,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMonLX9" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>