mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-26 00:29:28 +00:00
Updated AtomBusMon pinout to match 6502, would allow piggy-backing in principle
Change-Id: Ib2c8b2c3fd55f7fbba9b7aecc3d2289ff3114305
This commit is contained in:
David Banks
parent
2ec8488190
commit
3c7fb3429e
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@ -19,9 +19,6 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
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</file>
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<file xil_pn:name="src/constraints.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
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@ -241,6 +238,9 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
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</file>
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<file xil_pn:name="src/AtomBusMon.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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@ -9,6 +9,8 @@
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#ifdef EMBEDDED_6502
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unsigned int disMem(unsigned int addr);
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enum
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{
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IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, IND, MARK3, ABS, ABSX, ABSY, IND16, IND1X
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@ -553,6 +555,77 @@ int lookupBreakpoint(char *params) {
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}
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void logCycleCount(int offsetLow, int offsetHigh) {
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unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
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unsigned long countSecs = count / 1000000;
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unsigned long countMicros = count % 1000000;
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log0("%02ld.%06ld: ", countSecs, countMicros);
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}
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void logMode(unsigned int mode) {
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int i;
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int first = 1;
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for (i = 0; i < UNDEFINED; i++) {
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if (mode & 1) {
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if (first) {
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log0("%s", modeStrings[i]);
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} else {
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log0(", %c%s", tolower(*modeStrings[i]), modeStrings[i] + 1);
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}
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first = 0;
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}
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mode >>= 1;
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}
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}
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void logTrigger(int trigger) {
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if (trigger >= 0 && trigger < NUM_TRIGGERS) {
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log0("trigger: %s", triggerStrings[trigger]);
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} else {
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log0("trigger: ILLEGAL");
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}
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}
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int logDetails() {
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unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
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unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
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unsigned int b_data = hwRead8(OFFSET_BW_BD);
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unsigned int mode = hwRead8(OFFSET_BW_M);
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unsigned int watch = mode & 8;
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// Convert from 4-bit compressed to 6 bit expanded mode representation
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if (watch) {
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mode = (mode & 7) << 3;
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}
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// Update the serial console
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if (mode & W_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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logMode(mode);
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log0(" hit at %04X", i_addr);
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if (mode & BW_MEM_MASK) {
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if (mode & W_MEM_MASK) {
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log0(" writing");
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} else {
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log0(" reading");
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}
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log0(" %04X = %02X\n", b_addr, b_data);
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if (mode & B_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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#ifdef EMBEDDED_6502
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if (mode & B_MEM_MASK) {
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// It's only safe to do this for brkpts, as it makes memory accesses
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disMem(i_addr);
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}
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#endif
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} else {
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log0("\n");
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}
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return watch;
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}
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#ifdef EMBEDDED_6502
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void loadData(unsigned int data) {
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int i;
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@ -671,77 +744,8 @@ unsigned int disassemble(unsigned int addr)
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unsigned int disMem(unsigned int addr) {
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loadAddr(addr);
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return disassemble(addr);
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}
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void logMode(unsigned int mode) {
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int i;
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int first = 1;
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for (i = 0; i < UNDEFINED; i++) {
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if (mode & 1) {
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if (first) {
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log0("%s", modeStrings[i]);
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} else {
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log0(", %c%s", tolower(*modeStrings[i]), modeStrings[i] + 1);
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}
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first = 0;
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}
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mode >>= 1;
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}
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}
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void logTrigger(int trigger) {
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if (trigger >= 0 && trigger < NUM_TRIGGERS) {
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log0("trigger: %s", triggerStrings[trigger]);
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} else {
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log0("trigger: ILLEGAL");
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}
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}
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void logCycleCount(int offsetLow, int offsetHigh) {
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unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
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unsigned long countSecs = count / 1000000;
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unsigned long countMicros = count % 1000000;
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log0("%02ld.%06ld: ", countSecs, countMicros);
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}
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int logDetails() {
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unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
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unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
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unsigned int b_data = hwRead8(OFFSET_BW_BD);
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unsigned int mode = hwRead8(OFFSET_BW_M);
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unsigned int watch = mode & 8;
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// Convert from 4-bit compressed to 6 bit expanded mode representation
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if (watch) {
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mode = (mode & 7) << 3;
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}
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// Update the serial console
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if (mode & W_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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logMode(mode);
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log0(" hit at %04X", i_addr);
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if (mode & BW_MEM_MASK) {
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if (mode & W_MEM_MASK) {
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log0(" writing");
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} else {
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log0(" reading");
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}
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log0(" %04X = %02X\n", b_addr, b_data);
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if (mode & B_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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if (mode & B_MEM_MASK) {
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// It's only safe to do this for brkpts, as it makes memory accesses
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disMem(i_addr);
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}
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} else {
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log0("\n");
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}
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return watch;
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}
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#endif
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void logAddr() {
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@ -23,7 +23,7 @@ F_CPU=15855484
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CC=avr-gcc
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OBJCOPY=avr-objcopy
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CFLAGS=-DLCD=1 -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
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CFLAGS=-DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
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OBJECTS=AtomBusMon.o hd44780.o status.o
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76
src/AtomBusMon.ucf
Normal file
76
src/AtomBusMon.ucf
Normal file
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@ -0,0 +1,76 @@
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NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
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#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
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NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
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#NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
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#NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
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#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
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#NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
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NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
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#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
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NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
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NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
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NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
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NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
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NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
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NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
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NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
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NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
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NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
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NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
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NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
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NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
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#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
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NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
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NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
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NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
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NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
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#NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
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#NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
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#NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
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#NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
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#NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
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#NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
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#NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
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#NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
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NET "RNW" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
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#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
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#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
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#NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
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#NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
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NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
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NET "nRST" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
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NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
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NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
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NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
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NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
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NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
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# I/O's for test connector
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#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
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NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
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NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
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NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
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# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
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# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
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# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
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# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
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# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
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# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
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# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
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@ -36,10 +36,10 @@ entity AtomBusMon is
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trig : in std_logic_vector(1 downto 0);
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-- HD44780 LCD
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lcd_rs : out std_logic;
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lcd_rw : out std_logic;
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lcd_e : out std_logic;
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lcd_db : inout std_logic_vector(7 downto 4);
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--lcd_rs : out std_logic;
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--lcd_rw : out std_logic;
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--lcd_e : out std_logic;
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--lcd_db : inout std_logic_vector(7 downto 4);
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-- AVR Serial Port
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avr_RxD : in std_logic;
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@ -68,16 +68,23 @@ begin
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mon : entity work.BusMonCore port map (
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clock49 => clock49,
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Addr => Addr,
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Data => (others => '0'),
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Phi2 => Phi2,
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RNW => RNW,
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Sync => Sync,
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Rdy => Rdy,
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nRST => nRST,
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Regs => (others => '0'),
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RdOut => open,
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WrOut => open,
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AddrOut => open,
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DataOut => open,
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DataIn => (others => '0'),
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trig => trig,
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lcd_rs => lcd_rs,
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lcd_rw => lcd_rw,
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lcd_e => lcd_e,
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lcd_db => lcd_db,
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lcd_rs => open,
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lcd_rw => open,
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lcd_e => open,
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lcd_db => open,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => sw1,
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@ -87,8 +94,7 @@ begin
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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Regs => (others => '0')
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tcclk => tcclk
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);
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end behavioral;
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@ -1,75 +0,0 @@
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NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
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NET "lcd_rs" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6847 pin 2
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NET "lcd_rw" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6847 pin 3
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NET "lcd_e" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6847 pin 4
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NET "lcd_db<4>" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6847 pin 5
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NET "lcd_db<5>" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6847 pin 6
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NET "lcd_db<6>" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6847 pin 7
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NET "lcd_db<7>" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6847 pin 8
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NET "avr_RxD" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6847 pin 9
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NET "avr_TxD" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6847 pin 10
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NET "trig<0>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6847 pin 18
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NET "trig<1>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6847 pin 19
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NET "nRST" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6847 pin 20
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NET "Addr<0>" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6847 pin 21
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NET "Addr<1>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6847 pin 22
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NET "Addr<2>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6847 pin 23
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NET "Addr<3>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6847 pin 24
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NET "Addr<4>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6847 pin 25
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NET "Addr<5>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6847 pin 26
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NET "Addr<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6847 pin 27
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NET "Addr<7>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6847 pin 28
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NET "Addr<8>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6847 pin 29
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NET "Addr<9>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6847 pin 30
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NET "Addr<10>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6847 pin 31
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NET "Addr<11>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6847 pin 32
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NET "Addr<12>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6847 pin 33
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NET "Addr<13>" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6847 pin 34
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NET "Addr<14>" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6847 pin 35
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NET "Addr<15>" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6847 pin 36
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NET "Phi2" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6847 pin 37
|
||||
NET "RNW" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6847 pin 38
|
||||
NET "Sync" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6847 pin 39
|
||||
NET "Rdy" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6847 pin 40
|
||||
|
||||
|
||||
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
||||
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
||||
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
||||
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
||||
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
||||
|
||||
|
||||
# I/O's for test connector
|
||||
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
|
||||
|
||||
|
||||
# NET "" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6847 pin 11
|
||||
# NET "" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6847 pin 12
|
||||
# NET "" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6847 pin 13
|
||||
# NET "" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6847 pin 14
|
||||
# NET "" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6847 pin 15
|
||||
# NET "" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6847 pin 16
|
||||
|
||||
|
||||
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
||||
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
||||
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
||||
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
||||
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
||||
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
||||
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user