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Z80: Revert T80a wrapper to previous version
Change-Id: I856a39c51305e99c3d8b32efe5be1f8ed8b2583f
This commit is contained in:
parent
e65951cfbb
commit
4ecd60065e
306
src/T80/T80a.vhd
306
src/T80/T80a.vhd
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@ -1,16 +1,7 @@
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-- ****
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-- T80(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 300 started tidyup
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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--
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-- Z80 compatible microprocessor core, asynchronous top level
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-- Z80 compatible microprocessor core, asynchronous top level
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--
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--
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-- Version : 0250
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-- Version : 0247a
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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@ -47,32 +38,28 @@
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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--
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-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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--
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--
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-- 0208 : First complete release
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-- 0208 : First complete release
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--
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--
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-- 0211 : Fixed interrupt cycle
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-- 0211 : Fixed interrupt cycle
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--
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--
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-- 0235 : Updated for T80 interface change
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-- 0235 : Updated for T80 interface change
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--
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--
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-- 0238 : Updated for T80 interface change
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-- 0238 : Updated for T80 interface change
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--
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--
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-- 0240 : Updated for T80 interface change
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-- 0240 : Updated for T80 interface change
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--
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--
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-- 0242 : Updated for T80 interface change
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-- 0242 : Updated for T80 interface change
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--
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--
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-- 0247 : Fixed bus req/ack cycle
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-- 0247 : Fixed bus req/ack cycle
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--
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-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
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--
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-- Bus signal logic changes from the ZX Spectrum Next were made by:
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--
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-- Fabio Belavenuto, Charlie Ingley
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--
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--
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-- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa (tujikawa@hat.hi-ho.ne.jp)
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-- Fixed IORQ_n, RD_n, WR_n bus timing
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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@ -81,37 +68,34 @@ use work.T80_Pack.all;
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entity T80a is
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entity T80a is
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generic(
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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IOWait : integer := 1 -- 0 => Single I/O cycle, 1 => Std I/O cycle
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);
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);
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port(
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port(
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-- DMB
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-- Additions
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TS : out std_logic_vector(2 downto 0);
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TS : out std_logic_vector(2 downto 0);
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Regs : out std_logic_vector(255 downto 0);
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Regs : out std_logic_vector(255 downto 0);
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PdcData : out std_logic_vector(7 downto 0);
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PdcData : out std_logic_vector(7 downto 0);
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CEN : in std_logic;
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Din : in std_logic_vector(7 downto 0);
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Dout : out std_logic_vector(7 downto 0);
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Den : out std_logic;
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-- Original Signals
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-- Original Signals
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RESET_n : in std_logic;
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RESET_n : in std_logic;
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R800_mode : in std_logic := '0';
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CLK_n : in std_logic;
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CLK_n : in std_logic;
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CEN : in std_logic;
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WAIT_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0)
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A : out std_logic_vector(15 downto 0);
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-- D : inout std_logic_vector(7 downto 0)
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Din : in std_logic_vector(7 downto 0);
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);
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Dout : out std_logic_vector(7 downto 0);
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Den : out std_logic
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);
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end T80a;
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end T80a;
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architecture rtl of T80a is
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architecture rtl of T80a is
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@ -124,55 +108,51 @@ architecture rtl of T80a is
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signal Write : std_logic;
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signal Write : std_logic;
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signal MREQ : std_logic;
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signal MREQ : std_logic;
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signal MReq_Inhibit : std_logic;
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signal MReq_Inhibit : std_logic;
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signal IReq_Inhibit : std_logic; -- 0247a
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signal Req_Inhibit : std_logic;
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signal Req_Inhibit : std_logic;
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signal RD : std_logic;
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signal RD : std_logic;
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signal MREQ_n_i : std_logic;
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signal MREQ_n_i : std_logic;
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signal MREQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add MREQ control
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signal IORQ_n_i : std_logic;
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signal IORQ_n_i : std_logic;
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signal IORQ_t1 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_int : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ interrupt control
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signal IORQ_int_inhibit : std_logic_vector(2 downto 0);
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signal RD_n_i : std_logic;
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signal RD_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal WR_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add WR control
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signal WR_n_j : std_logic; -- 0247a
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signal RFSH_n_i : std_logic;
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signal RFSH_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal A_i : std_logic_vector(15 downto 0);
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signal A_i : std_logic_vector(15 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal Wait_s : std_logic;
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signal Wait_s : std_logic;
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signal MCycle : std_logic_vector(2 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal HALT_n_int : std_logic;
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signal HALT_n_int : std_logic;
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signal iack1 : std_logic;
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signal iack2 : std_logic;
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begin
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begin
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BUSAK_n <= BUSAK_n_i; -- 30/10/19 Charlie Ingley - IORQ/RD/WR changes
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MREQ_rw <= MREQ and (Req_Inhibit or MReq_Inhibit); -- added MREQ timing control
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BUSAK_n <= BUSAK_n_i;
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MREQ_n_i <= not MREQ_rw; -- changed MREQ generation
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MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
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IORQ_rw <= IORQ and not (IORQ_t1 or IORQ_t2); -- added IORQ generation timing control
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RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
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IORQ_n_i <= not ((IORQ_int and not IORQ_int_inhibit(2)) or IORQ_rw); -- changed IORQ generation
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WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
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RD_n_i <= not (RD and (MREQ_rw or IORQ_rw)); -- changed RD/IORQ generation
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WR_n_i <= not (Write and ((WR_t2 and MREQ_rw) or IORQ_rw)); -- added WR/IORQ timing control
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HALT_n <= HALT_n_int;
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HALT_n <= HALT_n_int;
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--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
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--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
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--MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
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--MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
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--IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
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--IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
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--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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--WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
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--WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
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--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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--D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
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MREQ_n <= MREQ_n_i;
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MREQ_n <= MREQ_n_i;
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IORQ_n <= IORQ_n_i;
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IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
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RD_n <= RD_n_i;
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RD_n <= RD_n_i;
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WR_n <= WR_n_i;
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WR_n <= WR_n_j; -- 0247a
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RFSH_n <= RFSH_n_i;
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RFSH_n <= RFSH_n_i;
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A <= A_i;
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A <= A_i;
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Dout <= DO;
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Dout <= DO;
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Den <= Write and BUSAK_n_i;
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Den <= Write and BUSAK_n_i;
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@ -181,18 +161,15 @@ begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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Reset_s <= '0';
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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Reset_s <= '1';
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Reset_s <= '1';
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end if;
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end if;
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end if;
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end process;
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end process;
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u0 : T80
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u0 : T80
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generic map(
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generic map(
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Mode => Mode,
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Mode => Mode,
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IOWait => IOWait)
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IOWait => 1)
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port map(
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port map(
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R800_mode => R800_mode,
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CEN => CEN,
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CEN => CEN,
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M1_n => M1_n,
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M1_n => M1_n,
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IORQ => IORQ,
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IORQ => IORQ,
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@ -214,7 +191,6 @@ begin
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MC => MCycle,
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MC => MCycle,
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TS => TState,
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TS => TState,
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IntCycle_n => IntCycle_n,
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IntCycle_n => IntCycle_n,
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-- DMB
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NMICycle_n => NMICycle_n,
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NMICycle_n => NMICycle_n,
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REG => Regs(211 downto 0),
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REG => Regs(211 downto 0),
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DIRSet => '0',
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DIRSet => '0',
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@ -235,72 +211,102 @@ begin
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end if;
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end if;
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end process;
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end process;
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-- 30/10/19 Charlie Ingley - Generate WR_t2 to correct MREQ/WR timing
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process (CLK_n) -- 0247a
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process (Reset_s,CLK_n)
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begin
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if CLK_n'event and CLK_n = '1' then
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IReq_Inhibit <= (not IORQ) and IntCycle_n;
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end if;
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end process;
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process (Reset_s,CLK_n) -- 0247a
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begin
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begin
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if Reset_s = '0' then
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if Reset_s = '0' then
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WR_t2 <= '0';
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WR_n_i <= '1';
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elsif CLK_n'event and CLK_n = '0' then
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if CEN = '1' then
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if MCycle /= "001" then
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if (IORQ = '0') then
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if TState = "010" then -- WR starts on falling edge of T2 for MREQ
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if TState = "010" then
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WR_t2 <= Write;
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WR_n_i <= not Write;
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elsif Tstate = "011" then
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WR_n_i <= '1';
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end if;
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else
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if TState = "001" then -- DMB
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WR_n_i <= not Write;
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elsif Tstate = "011" then
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WR_n_i <= '1';
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end if;
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end if;
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end if;
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end if;
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if TState = "011" then -- end WR
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end if;
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WR_t2 <= '0';
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end if;
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end process;
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process (Reset_s,CLK_n) -- 0247a
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begin
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if Reset_s = '0' then
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Req_Inhibit <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if MCycle = "001" and TState = "010" and wait_s = '1' then
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Req_Inhibit <= '1';
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else
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Req_Inhibit <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Generate Req_Inhibit
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process (Reset_s,CLK_n)
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process (Reset_s,CLK_n)
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begin
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begin
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if Reset_s = '0' then
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if Reset_s = '0' then
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Req_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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MReq_Inhibit <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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Req_Inhibit <= '0';
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else
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Req_Inhibit <= '1';
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end if;
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end if;
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end if;
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end process;
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-- Generate MReq_Inhibit
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process (Reset_s, CLK_n)
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begin
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if Reset_s = '0' then
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MReq_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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elsif CLK_n'event and CLK_n = '0' then
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if CEN = '1' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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if MCycle = "001" and TState = "010" then
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MReq_Inhibit <= '0';
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else
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MReq_Inhibit <= '1';
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MReq_Inhibit <= '1';
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else
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MReq_Inhibit <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Generate RD for MREQ
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process(Reset_s,CLK_n) -- 0247a
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process(Reset_s,CLK_n)
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begin
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begin
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if Reset_s = '0' then
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if Reset_s = '0' then
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RD <= '0';
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RD <= '0';
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IORQ_n_i <= '1';
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MREQ <= '0';
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MREQ <= '0';
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iack1 <= '0';
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iack2 <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if CEN = '1' then
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if MCycle = "001" then
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if MCycle = "001" then
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||||||
if TState = "001" then
|
if IntCycle_n = '1' then
|
||||||
RD <= IntCycle_n;
|
-- Normal M1 Cycle
|
||||||
MREQ <= IntCycle_n;
|
if TState = "001" then
|
||||||
|
RD <= '1';
|
||||||
|
MREQ <= '1';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
-- Interupt Ack Cycle
|
||||||
|
-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
|
||||||
|
-- Assert IORQ in middle of third T1
|
||||||
|
if TState = "001" then
|
||||||
|
iack1 <= '1';
|
||||||
|
iack2 <= iack1;
|
||||||
|
else
|
||||||
|
iack1 <= '0';
|
||||||
|
iack2 <= '0';
|
||||||
|
end if;
|
||||||
|
if iack2 = '1' then
|
||||||
|
IORQ_n_i <= '0';
|
||||||
|
end if;
|
||||||
end if;
|
end if;
|
||||||
if TState = "011" then
|
if TState = "011" then
|
||||||
RD <= '0';
|
RD <= '0';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
MREQ <= '1';
|
MREQ <= '1';
|
||||||
end if;
|
end if;
|
||||||
if TState = "100" then
|
if TState = "100" then
|
||||||
|
@ -308,11 +314,13 @@ begin
|
||||||
end if;
|
end if;
|
||||||
else
|
else
|
||||||
if TState = "001" and NoRead = '0' then
|
if TState = "001" and NoRead = '0' then
|
||||||
RD <= not Write;
|
IORQ_n_i <= not IORQ;
|
||||||
MREQ <= not IORQ;
|
MREQ <= not IORQ;
|
||||||
|
RD <= not Write; -- DMB
|
||||||
end if;
|
end if;
|
||||||
if TState = "011" then
|
if TState = "011" then
|
||||||
RD <= '0';
|
RD <= '0';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
MREQ <= '0';
|
MREQ <= '0';
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
@ -320,74 +328,6 @@ begin
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
-- 30/10/19 Charlie Ingley - Generate IORQ_int for IORQ interrupt timing control
|
|
||||||
process(Reset_s,CLK_n)
|
|
||||||
begin
|
|
||||||
if Reset_s = '0' then
|
|
||||||
IORQ_int <= '0';
|
|
||||||
elsif CLK_n'event and CLK_n = '1' then
|
|
||||||
if CEN = '1' then
|
|
||||||
if MCycle = "001" then
|
|
||||||
if TState = "001" then
|
|
||||||
IORQ_int <= not IntCycle_n;
|
|
||||||
end if;
|
|
||||||
if TState = "010" then
|
|
||||||
IORQ_int <= '0';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
process(Reset_s,CLK_n)
|
|
||||||
begin
|
|
||||||
if Reset_s = '0' then
|
|
||||||
IORQ_int_inhibit <= "111";
|
|
||||||
elsif CLK_n'event and CLK_n = '0' then
|
|
||||||
if CEN = '1' then
|
|
||||||
if IntCycle_n = '0' then
|
|
||||||
if MCycle = "001" then
|
|
||||||
IORQ_int_inhibit <= IORQ_int_inhibit(1 downto 0) & '0';
|
|
||||||
end if;
|
|
||||||
if MCycle = "010" then
|
|
||||||
IORQ_int_inhibit <= "111";
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t1 for IORQ timing control
|
|
||||||
process(Reset_s, CLK_n)
|
|
||||||
begin
|
|
||||||
if Reset_s = '0' then
|
|
||||||
IORQ_t1 <= '1';
|
|
||||||
elsif CLK_n'event and CLK_n = '0' then
|
|
||||||
if CEN = '1' then
|
|
||||||
if TState = "001" then
|
|
||||||
IORQ_t1 <= not IntCycle_n;
|
|
||||||
end if;
|
|
||||||
if TState = "011" then
|
|
||||||
IORQ_t1 <= '1';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t2 for IORQ timing control
|
|
||||||
process (RESET_n, CLK_n)
|
|
||||||
begin
|
|
||||||
if RESET_n = '0' then
|
|
||||||
IORQ_t2 <= '1';
|
|
||||||
elsif CLK_n'event and CLK_n = '1' then
|
|
||||||
if CEN = '1' then
|
|
||||||
IORQ_t2 <= IORQ_t1;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
-- DMB
|
|
||||||
|
|
||||||
TS <= TState;
|
TS <= TState;
|
||||||
|
|
||||||
PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
|
PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
|
||||||
|
|
Loading…
Reference in New Issue
Block a user