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https://github.com/hoglet67/AtomBusMon.git
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z80: generate RFSH_n cycles when stopped
Change-Id: Ice9a78932bda74098cdde8d0a5571bc4bb784bb4
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@ -99,6 +99,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
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signal WR_n_int : std_logic;
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signal MREQ_n_int : std_logic;
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signal IORQ_n_int : std_logic;
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signal RFSH_n_int : std_logic;
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signal M1_n_int : std_logic;
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signal WAIT_n_int : std_logic;
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signal TState : std_logic_vector(2 downto 0);
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@ -125,6 +126,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
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signal memory_wr1 : std_logic;
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signal mon_mreq_n : std_logic;
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signal mon_iorq_n : std_logic;
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signal mon_rfsh_n : std_logic;
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signal mon_rd_n : std_logic;
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signal mon_wr_n : std_logic;
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signal mon_wait_n : std_logic;
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@ -271,7 +273,7 @@ begin
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IORQ_n => IORQ_n_int,
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RD_n => RD_n_int,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n,
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RFSH_n => RFSH_n_int,
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HALT_n => HALT_n,
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BUSAK_n => BUSAK_n,
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A => Addr_int,
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@ -386,6 +388,7 @@ begin
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MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n;
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IORQ_n <= IORQ_n_int when state = idle else mon_iorq_n;
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RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n;
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WR_n <= WR_n_int when state = idle else mon_wr_n;
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RD_n <= RD_n_int when state = idle else mon_rd_n;
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M1_n <= M1_n_int when state = idle else '1';
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@ -414,6 +417,7 @@ begin
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io_rd1 <= '0';
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io_wr1 <= '0';
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SS_Step_held <= '0';
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mon_rfsh_n <= '1';
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elsif rising_edge(CLK_n) then
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@ -465,10 +469,12 @@ begin
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-- Increment the refresh address (7 bits, just like the Z80)
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rfsh_addr(6 downto 0) <= rfsh_addr(6 downto 0) + 1;
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when nop_t2 =>
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mon_rfsh_n <= '0';
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state <= nop_t3;
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when nop_t3 =>
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state <= nop_t4;
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when nop_t4 =>
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mon_rfsh_n <= '1';
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if memory_wr1 = '1' or io_wr1 = '1' then
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state <= wr_t1;
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io_not_mem <= io_wr1;
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