6502: Update T65 to latest version (same as AtomFpga)
Change-Id: I580c5aff7bd4c7cd234f82c25519a081d20b239f
This commit is contained in:
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cd89e92a16
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5699d02d3d
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@ -1,32 +1,65 @@
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-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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-- Ver 313 WoS January 2015
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-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
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-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
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-- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
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--
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-- Ver 312 WoS January 2015
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-- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
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-- Added comments in MCode section to find handling of individual opcodes more easily
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-- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with
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-- actual FPGAARCADE C64 core (sources used: SVN version 1021).
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--
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-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
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-- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
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-- SAX opcode
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-- SHA opcode
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-- SHX opcode
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-- SHY opcode
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-- SHS opcode
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-- LAS opcode
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-- alternate SBC opcode
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-- fixed NOP with immediate param (caused Lorenz trap test to fail)
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-- IRQ and NMI timing fixes (in conjuction with branches)
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--
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-- Ver 304 WoS December 2014
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-- Undoc opcode fixes:
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-- ARR opcode
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-- ANE/XAA opcode
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-- Corrected issue with NMI/IRQ prio (when asserted the same time)
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--
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-- Ver 303 ost(ML) July 2014
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-- (Sorry for some scratchpad comments that may make little sense)
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-- Mods and some 6502 undocumented instructions.
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--
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-- Not correct opcodes acc. to Lorenz tests (incomplete list):
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-- Not correct opcodes acc. to Lorenz tests (incomplete list):
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-- NOPN (nop)
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-- NOPZX (nop + byte 172)
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-- NOPAX (nop + word da ... da: byte 0)
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-- ASOZ (byte $07 + byte 172)
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--
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-- Wolfgang April 2014
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-- Ver 303 Bugfixes for NMI from foft
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-- Ver 302 Bugfix for BRK command
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-- Wolfgang January 2014
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-- Ver 301 more merging
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-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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-- Ver 303,302 WoS April 2014
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-- Bugfixes for NMI from foft
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-- Bugfix for BRK command (and its special flag)
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--
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-- Ver 300,301 WoS January 2014
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-- More merging
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-- Bugfixes by ehenciak added, started tidyup *bust*
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--
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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-- ****
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--
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-- 65xx compatible microprocessor core
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--
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-- Version : 0246
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-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002...2015
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-- Daniel Wallner (jesus <at> opencores <dot> org)
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-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
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-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
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-- Morten Leikvoll ()
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--
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-- All rights reserved
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--
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@ -56,22 +89,37 @@
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author(s), but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t65/
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-- ----- IMPORTANT NOTES -----
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--
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-- Limitations :
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-- Limitations:
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-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
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-- 65C02 supported : inc, dec, phx, plx, phy, ply
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-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
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-- Some interface signals behave incorrect
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-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
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--
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-- 65C02 and 65C816 modes are incomplete
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-- Undocumented instructions are not supported
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-- Some interface signals behaves incorrect
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-- Usage:
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-- The enable signal allows clock gating / throttling without using the ready signal.
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-- Set it to constant '1' when using the Clk input as the CPU clock directly.
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--
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-- File history :
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-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
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-- otherwise some undocumented opcodes won't work correctly.
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-- EXAMPLE:
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-- CPU : entity work.T65
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-- port map (
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-- R_W_n => cpu_rwn_s,
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-- [....all other ports....]
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-- DI => cpu_din_s,
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-- DO => cpu_dout_s
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-- );
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-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
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-- [....other sources from peripherals and memories...]
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--
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-- 0246 : First release
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-- ----- IMPORTANT NOTES -----
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--
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library IEEE;
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@ -79,8 +127,6 @@ library IEEE;
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use IEEE.numeric_std.all;
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use work.T65_Pack.all;
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-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
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-- the ready signal to limit the CPU.
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entity T65 is
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
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@ -102,17 +148,18 @@ entity T65 is
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VDA : out std_logic;
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VPA : out std_logic;
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A : out std_logic_vector(23 downto 0);
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DI : in std_logic_vector(7 downto 0);--NOTE:Make sure DI equals DO when writing. This is important for DCP/DCM undoc instruction. TODO:convert to inout
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
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Regs : out std_logic_vector(63 downto 0)
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Regs : out std_logic_vector(63 downto 0);
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DEBUG : out T_t65_dbg
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);
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end T65;
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architecture rtl of T65 is
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-- Registers
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signal ABC, X, Y, D : std_logic_vector(15 downto 0);
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signal ABC, X, Y : std_logic_vector(15 downto 0);
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signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
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signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
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signal BAH : std_logic_vector(7 downto 0);
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@ -149,6 +196,7 @@ architecture rtl of T65 is
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signal BusA : std_logic_vector(7 downto 0);
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signal BusA_r : std_logic_vector(7 downto 0);
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signal BusB : std_logic_vector(7 downto 0);
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signal BusB_r : std_logic_vector(7 downto 0);
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signal ALU_Q : std_logic_vector(7 downto 0);
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signal P_Out : std_logic_vector(7 downto 0);
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@ -178,37 +226,39 @@ architecture rtl of T65 is
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signal LDBAH : std_logic;
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signal SaveP : std_logic;
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signal Write : std_logic;
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signal ALUmore : std_logic;
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signal really_rdy : std_logic;
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signal R_W_n_i : std_logic;
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signal R_W_n_i_d : std_logic;
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signal NMIActClear : std_logic; -- MWW hack
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signal Res_n_i : std_logic;
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signal Res_n_d : std_logic;
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signal really_rdy : std_logic;
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signal WRn_i : std_logic;
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signal NMI_entered : std_logic;
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begin
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-- workaround for ready-handling
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-- ehenciak : Drive R_W_n_i off chip.
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R_W_n <= R_W_n_i;
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-- ehenciak : gate Rdy with read/write to make an "OK, it's
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-- really OK to stop the processor now if Rdy is
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-- deasserted" signal
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really_rdy <= Rdy or not(R_W_n_i);
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----
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-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
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really_rdy <= Rdy or not(WRn_i);
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Sync <= '1' when MCycle = "000" else '0';
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EF <= EF_i;
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MF <= MF_i;
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XF <= XF_i;
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R_W_n <= WRn_i;
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ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
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VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
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VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; -- Incorrect !!!!!!!!!!!!
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VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
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VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
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VPA <= '1' when Jump(1) = '0' else '0';
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Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
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-- debugging signals
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DEBUG.I <= IR;
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DEBUG.A <= ABC(7 downto 0);
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DEBUG.X <= X(7 downto 0);
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DEBUG.Y <= Y(7 downto 0);
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DEBUG.S <= std_logic_vector(S(7 downto 0));
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DEBUG.P <= P;
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mcode : T65_MCode
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Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
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mcode : entity work.T65_MCode
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port map(
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--inputs
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Mode => Mode_r,
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@ -240,11 +290,10 @@ begin
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LDBAL => LDBAL,
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LDBAH => LDBAH,
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SaveP => SaveP,
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ALUmore => ALUmore,
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Write => Write
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);
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alu : T65_ALU
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alu : entity work.T65_ALU
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port map(
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Mode => Mode_r,
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Op => ALU_Op_r,
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@ -255,14 +304,25 @@ begin
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Q => ALU_Q
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);
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-- the 65xx design requires at least two clock cycles before
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-- starting its reset sequence (according to datasheet)
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process (Res_n, Clk)
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begin
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if Res_n = '0' then
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Res_n_i <= '0';
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Res_n_d <= '0';
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elsif Clk'event and Clk = '1' then
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Res_n_i <= Res_n_d;
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Res_n_d <= '1';
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end if;
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end process;
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process (Res_n_i, Clk)
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begin
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if Res_n_i = '0' then
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PC <= (others => '0'); -- Program Counter
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IR <= "00000000";
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S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
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D <= (others => '0');
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S <= (others => '0'); -- Dummy
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PBR <= (others => '0');
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DBR <= (others => '0');
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@ -271,7 +331,7 @@ begin
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Write_Data_r <= Write_Data_DL;
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Set_Addr_To_r <= Set_Addr_To_PBR;
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R_W_n_i <= '1';
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WRn_i <= '1';
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EF_i <= '1';
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MF_i <= '1';
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XF_i <= '1';
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@ -279,9 +339,8 @@ begin
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elsif Clk'event and Clk = '1' then
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if (Enable = '1') then
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if (really_rdy = '1') then
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R_W_n_i <= not Write or RstCycle;
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WRn_i <= not Write or RstCycle;
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D <= (others => '1'); -- Dummy
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PBR <= (others => '1'); -- Dummy
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DBR <= (others => '1'); -- Dummy
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EF_i <= '0'; -- Dummy
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@ -300,6 +359,10 @@ begin
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else
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IR <= DI;
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end if;
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if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
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S(7 downto 0) <= unsigned(ALU_Q);
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end if;
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end if;
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ALU_Op_r <= ALU_Op;
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@ -316,9 +379,6 @@ begin
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if Dec_S = '1' and RstCycle = '0' then
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S <= S - 1;
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end if;
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if LDS = '1' then
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S(7 downto 0) <= unsigned(ALU_Q);
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end if;
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if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
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PC <= PC + 1;
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@ -329,10 +389,8 @@ begin
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case Jump is
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when "01" =>
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PC <= PC + 1;
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when "10" =>
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PC <= unsigned(DI & DL);
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when "11" =>
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if PCAdder(8) = '1' then
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if DL(7) = '0' then
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@ -342,7 +400,6 @@ begin
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end if;
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end if;
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PC(7 downto 0) <= PCAdder(7 downto 0);
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when others => null;
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end case;
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end if;
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@ -353,13 +410,13 @@ begin
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PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
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else "0" & PC(7 downto 0);
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process (Res_n, Clk)
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variable tmpP:std_logic_vector(7 downto 0);--ML:Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
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process (Res_n_i, Clk)
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variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
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begin
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if Res_n = '0' then
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P <= x"00"; -- ensure we have nothing set on reset (e.g. B flag!)
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if Res_n_i = '0' then
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P <= x"00"; -- ensure we have nothing set on reset
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elsif Clk'event and Clk = '1' then
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tmpP:=P;
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tmpP:=P;
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if (Enable = '1') then
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if (really_rdy = '1') then
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if MCycle = "000" then
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@ -373,82 +430,59 @@ begin
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Y(7 downto 0) <= ALU_Q;
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end if;
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if (LDA or LDX or LDY) = '1' then
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-- P <= P_Out;-- Replaced with:
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tmpP:=P_Out;
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end if;
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end if;
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if SaveP = '1' then
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-- P <= P_Out;-- Replaced with:
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tmpP:=P_Out;
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end if;
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if LDP = '1' then
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-- P <= ALU_Q;-- Replaced with: --ML:no need anymore: AND x"EF"; -- NEVER set B on RTI and PLP
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tmpP:=ALU_Q;
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end if;
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if IR(4 downto 0) = "11000" then
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case IR(7 downto 5) is
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when "000" =>--0x18(clc)
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-- P(Flag_C) <= '0';-- Replaced with:
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tmpP(Flag_C) := '0';
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when "001" =>--0x38(sec)
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-- P(Flag_C) <= '1';
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tmpP(Flag_C) := '1';
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when "010" =>--0x58(cli)
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-- P(Flag_I) <= '0';
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tmpP(Flag_I) := '0';
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when "011" =>--0x78(sei)
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-- P(Flag_I) <= '1';
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tmpP(Flag_I) := '1';
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when "101" =>--0xb8(clv)
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-- P(Flag_V) <= '0';
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tmpP(Flag_V) := '0';
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when "110" =>--0xd8(cld)
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-- P(Flag_D) <= '0';
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tmpP(Flag_D) := '0';
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when "111" =>--0xf8(sed)
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-- P(Flag_D) <= '1';
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tmpP(Flag_D) := '1';
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when others =>
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end case;
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end if;
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--ML:Removed change of B flag, its constant '1' in P
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--ML:The B flag appears to be locked to '1', but when pushed to stack, the SR data on the stack has the B flag cleared on interrupts, set on BRK instr.
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--ML:The state of the B flag on warm reset apparently is unchanged (not confirmed, please do if you know)
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--ML:The state of the B flag on cold reset is uncertain, but my guess would be set, unless it can be used to detect cold from warm reset.
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--Since we cant (well, won't) simulate B=0 on cold reset, we just behave as if it was constant 1.
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-- P(Flag_B) <= '1';
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tmpP(Flag_B) := '1';
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-- if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then -- BRK
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-- P(Flag_B) <= '1';
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-- elsif IR = "00001000" then -- PHP
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-- P(Flag_B) <= '1';
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-- else
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-- P(Flag_B) <= '0'; --> not the best way, but we keep B zero except for BRK and PHP opcodes
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-- end if;
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if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --and (NMICycle = '1' or IRQCycle = '1') then
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if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
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--This should happen after P has been pushed to stack
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-- P(Flag_I) <= '1';
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tmpP(Flag_I) := '1';
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end if;
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if SO_n_o = '1' and SO_n = '0' then
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-- P(Flag_V) <= '1';
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tmpP(Flag_V) := '1';
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end if;
|
||||
if RstCycle = '1' then
|
||||
-- P(Flag_I) <= '0';
|
||||
-- P(Flag_D) <= '0';
|
||||
tmpP(Flag_I) := '1';
|
||||
tmpP(Flag_D) := '0';
|
||||
end if;
|
||||
-- P(Flag_1) <= '1';
|
||||
tmpP(Flag_1) := '1';
|
||||
|
||||
P<=tmpP;--new way
|
||||
|
||||
SO_n_o <= SO_n;
|
||||
IRQ_n_o <= IRQ_n;
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
|
||||
IRQ_n_o <= IRQ_n;
|
||||
end if;
|
||||
end if;
|
||||
-- detect nmi even if not rdy
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
|
||||
NMI_n_o <= NMI_n;
|
||||
end if;
|
||||
NMI_n_o <= NMI_n; -- MWW: detect nmi even if not rdy
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
@ -459,24 +493,26 @@ begin
|
|||
--
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
process (Res_n, Clk)
|
||||
process (Res_n_i, Clk)
|
||||
begin
|
||||
if Res_n = '0' then
|
||||
if Res_n_i = '0' then
|
||||
BusA_r <= (others => '0');
|
||||
BusB <= (others => '0');
|
||||
BusB_r <= (others => '0');
|
||||
AD <= (others => '0');
|
||||
BAL <= (others => '0');
|
||||
BAH <= (others => '0');
|
||||
DL <= (others => '0');
|
||||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
NMI_entered <= '0';
|
||||
if (really_rdy = '1') then
|
||||
--if (Rdy = '1') then
|
||||
BusA_r <= BusA;
|
||||
if ALUmore='1' then
|
||||
BusB <= ALU_Q;
|
||||
else
|
||||
BusB <= DI;
|
||||
BusB <= DI;
|
||||
|
||||
-- not really nice, but no better way found yet !
|
||||
if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
|
||||
BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
|
||||
end if;
|
||||
|
||||
case BAAdd is
|
||||
|
@ -495,26 +531,25 @@ begin
|
|||
when others =>
|
||||
end case;
|
||||
|
||||
-- ehenciak : modified to use Y register as well (bugfix)
|
||||
-- modified to use Y register as well
|
||||
if ADAdd = '1' then
|
||||
if (AddY = '1') then
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
|
||||
else
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
NMIActClear <= '0';
|
||||
if IR = "00000000" then
|
||||
BAL <= (others => '1');
|
||||
BAH <= (others => '1');
|
||||
if RstCycle = '1' then
|
||||
BAL(2 downto 0) <= "100";
|
||||
elsif NMICycle = '1' then
|
||||
BAL(2 downto 0) <= "100";
|
||||
elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
|
||||
BAL(2 downto 0) <= "010";
|
||||
elsif NMIAct = '1' then -- MWW, force this to be changed by NMI, even if in midstream IRQ/brk
|
||||
BAL(2 downto 0) <= "010";
|
||||
NMIActClear <= '1';
|
||||
if MCycle="100" then
|
||||
NMI_entered <= '1';
|
||||
end if;
|
||||
else
|
||||
BAL(2 downto 0) <= "110";
|
||||
end if;
|
||||
|
@ -523,7 +558,6 @@ begin
|
|||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
if LDDI = '1' then
|
||||
DL <= DI;
|
||||
end if;
|
||||
|
@ -554,16 +588,20 @@ begin
|
|||
Y(7 downto 0) when Set_BusA_To_Y,
|
||||
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
|
||||
P when Set_BusA_To_P,
|
||||
ABC(7 downto 0) and DI when Set_BusA_To_DA,
|
||||
(ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
|
||||
(ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
|
||||
ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA
|
||||
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
|
||||
|
||||
with Set_Addr_To_r select
|
||||
A <=
|
||||
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_S,
|
||||
DBR & "00000000" & AD when Set_Addr_To_AD,
|
||||
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP,
|
||||
DBR & "00000000" & AD when Set_Addr_To_ZPG,
|
||||
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
|
||||
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
|
||||
|
||||
--ML:This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
|
||||
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
|
||||
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
|
||||
|
||||
with Write_Data_r select
|
||||
|
@ -576,6 +614,10 @@ begin
|
|||
PwithB when Write_Data_P,
|
||||
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
|
||||
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
|
||||
ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX,
|
||||
ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
|
||||
X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
|
||||
Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
|
||||
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
|
||||
|
||||
|
||||
|
@ -585,9 +627,9 @@ begin
|
|||
--
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
process (Res_n, Clk)
|
||||
process (Res_n_i, Clk)
|
||||
begin
|
||||
if Res_n = '0' then
|
||||
if Res_n_i = '0' then
|
||||
MCycle <= "001";
|
||||
RstCycle <= '1';
|
||||
IRQCycle <= '0';
|
||||
|
@ -596,31 +638,29 @@ begin
|
|||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
if (really_rdy = '1') then
|
||||
if (NMIActClear = '1') then
|
||||
NMIAct <= '0';
|
||||
end if;
|
||||
|
||||
if MCycle = LCycle or Break = '1' then
|
||||
MCycle <= "000";
|
||||
RstCycle <= '0';
|
||||
IRQCycle <= '0';
|
||||
NMICycle <= '0';
|
||||
if NMIAct = '1' then
|
||||
if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
|
||||
NMICycle <= '1';
|
||||
NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
|
||||
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
|
||||
IRQCycle <= '1';
|
||||
end if;
|
||||
else
|
||||
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
|
||||
end if;
|
||||
|
||||
if NMICycle = '1' then
|
||||
NMIAct <= '0';
|
||||
end if;
|
||||
end if;
|
||||
if NMI_n_o = '1' and NMI_n = '0' then -- MWW: detect nmi even if not rdy
|
||||
end if;
|
||||
--detect NMI even if not rdy
|
||||
if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
|
||||
NMIAct <= '1';
|
||||
end if;
|
||||
-- we entered NMI during BRK instruction
|
||||
if NMI_entered='1' then
|
||||
NMIAct <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
|
|
@ -1,20 +1,18 @@
|
|||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 303 ost(ML) July 2014
|
||||
-- ALU opcodes to vhdl types
|
||||
-- Ver 300 Bugfixes by ehenciak added
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
-- See list of changes in T65 top file (T65.vhd)...
|
||||
--
|
||||
-- ****
|
||||
-- 65xx compatible microprocessor core
|
||||
--
|
||||
-- 6502 compatible microprocessor core
|
||||
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
|
||||
--
|
||||
-- Version : 0245
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
-- Copyright (c) 2002...2015
|
||||
-- Daniel Wallner (jesus <at> opencores <dot> org)
|
||||
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
|
||||
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
|
||||
-- Morten Leikvoll ()
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
|
@ -44,19 +42,12 @@
|
|||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- Please report bugs to the author(s), but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t65/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0245 : First version
|
||||
--
|
||||
-- See in T65 top file (T65.vhd)...
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
@ -88,6 +79,7 @@ architecture rtl of T65_ALU is
|
|||
signal SBC_V : std_logic;
|
||||
signal SBC_N : std_logic;
|
||||
signal SBC_Q : std_logic_vector(7 downto 0);
|
||||
signal SBX_Q : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
|
@ -146,7 +138,7 @@ begin
|
|||
Op=ALU_OP_SBC or --"0111"
|
||||
Op=ALU_OP_ROL or --"1001"
|
||||
Op=ALU_OP_ROR or --"1011"
|
||||
Op=ALU_OP_EQ3 or --"1101"
|
||||
-- Op=ALU_OP_EQ3 or --"1101"
|
||||
Op=ALU_OP_INC --"1111"
|
||||
) then
|
||||
CT:='1';
|
||||
|
@ -156,10 +148,10 @@ begin
|
|||
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
|
||||
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
|
||||
|
||||
-- pragma translate_off
|
||||
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
|
||||
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
|
||||
-- pragma translate_on
|
||||
-- pragma translate_off
|
||||
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
|
||||
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
|
||||
-- pragma translate_on
|
||||
|
||||
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
|
||||
SBC_Z <= '1';
|
||||
|
@ -171,6 +163,8 @@ begin
|
|||
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
|
||||
SBC_N <= AH(4);
|
||||
|
||||
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
|
||||
if P_In(Flag_D) = '1' then
|
||||
if AL(5) = '1' then
|
||||
AL(5 downto 1) := AL(5 downto 1) - 6;
|
||||
|
@ -186,79 +180,114 @@ begin
|
|||
|
||||
process (Op, P_In, BusA, BusB,
|
||||
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
|
||||
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
|
||||
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
|
||||
SBX_Q)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable Q2_t : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
|
||||
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
|
||||
P_Out <= P_In;
|
||||
Q_t := BusA;
|
||||
Q_t := BusA;
|
||||
Q2_t := BusA;
|
||||
case Op is
|
||||
when ALU_OP_OR=>
|
||||
Q_t := BusA or BusB;
|
||||
when ALU_OP_AND=>
|
||||
Q_t := BusA and BusB;
|
||||
when ALU_OP_EOR=>
|
||||
Q_t := BusA xor BusB;
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_V) <= ADC_V;
|
||||
P_Out(Flag_C) <= ADC_C;
|
||||
Q_t := ADC_Q;
|
||||
when ALU_OP_EQ2|ALU_OP_EQ3=>
|
||||
-- LDA
|
||||
when ALU_OP_CMP=>
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
when ALU_OP_SBC=>
|
||||
P_Out(Flag_V) <= SBC_V;
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
Q_t := SBC_Q;
|
||||
when ALU_OP_ASL=>
|
||||
Q_t := BusA(6 downto 0) & "0";
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_ROL=>
|
||||
Q_t := BusA(6 downto 0) & P_In(Flag_C);
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_LSR=>
|
||||
Q_t := "0" & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_ROR=>
|
||||
Q_t := P_In(Flag_C) & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_V) <= BusB(6);
|
||||
when ALU_OP_DEC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) - 1);
|
||||
when ALU_OP_INC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) + 1);
|
||||
when others =>
|
||||
--EQ1,EQ2,EQ3 passes BusA to Q_t
|
||||
when ALU_OP_OR=>
|
||||
Q_t := BusA or BusB;
|
||||
when ALU_OP_AND=>
|
||||
Q_t := BusA and BusB;
|
||||
when ALU_OP_EOR=>
|
||||
Q_t := BusA xor BusB;
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_V) <= ADC_V;
|
||||
P_Out(Flag_C) <= ADC_C;
|
||||
Q_t := ADC_Q;
|
||||
when ALU_OP_CMP=>
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
when ALU_OP_SAX=>
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate)
|
||||
when ALU_OP_SBC=>
|
||||
P_Out(Flag_V) <= SBC_V;
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction
|
||||
when ALU_OP_ASL=>
|
||||
Q_t := BusA(6 downto 0) & "0";
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_ROL=>
|
||||
Q_t := BusA(6 downto 0) & P_In(Flag_C);
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_LSR=>
|
||||
Q_t := "0" & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_ROR=>
|
||||
Q_t := P_In(Flag_C) & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_ARR=>
|
||||
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
|
||||
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
|
||||
Q2_t := Q_t;
|
||||
if P_In(Flag_D)='1' then
|
||||
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
|
||||
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
|
||||
end if;
|
||||
if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
|
||||
Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
|
||||
P_Out(Flag_C) <= '1';
|
||||
else
|
||||
P_Out(Flag_C) <= '0';
|
||||
end if;
|
||||
else
|
||||
P_Out(Flag_C) <= Q_t(6);
|
||||
end if;
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_V) <= BusB(6);
|
||||
when ALU_OP_DEC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) - 1);
|
||||
when ALU_OP_INC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) + 1);
|
||||
when others =>
|
||||
null;
|
||||
--EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
|
||||
end case;
|
||||
|
||||
case Op is
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_N) <= ADC_N;
|
||||
P_Out(Flag_Z) <= ADC_Z;
|
||||
when ALU_OP_CMP|ALU_OP_SBC=>
|
||||
P_Out(Flag_N) <= SBC_N;
|
||||
P_Out(Flag_Z) <= SBC_Z;
|
||||
when ALU_OP_EQ1=>
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_N) <= BusB(7);
|
||||
if (BusA and BusB) = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
P_Out(Flag_N) <= Q_t(7);
|
||||
if Q_t = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_N) <= ADC_N;
|
||||
P_Out(Flag_Z) <= ADC_Z;
|
||||
when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
|
||||
P_Out(Flag_N) <= SBC_N;
|
||||
P_Out(Flag_Z) <= SBC_Z;
|
||||
when ALU_OP_EQ1=>--dont touch P
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_N) <= BusB(7);
|
||||
if (BusA and BusB) = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when ALU_OP_ANC=>
|
||||
P_Out(Flag_N) <= Q_t(7);
|
||||
P_Out(Flag_C) <= Q_t(7);
|
||||
if Q_t = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
P_Out(Flag_N) <= Q_t(7);
|
||||
if Q_t = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
Q <= Q_t;
|
||||
if Op=ALU_OP_ARR then
|
||||
-- handled above in ARR code
|
||||
Q <= Q2_t;
|
||||
else
|
||||
Q <= Q_t;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,20 +1,18 @@
|
|||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 303 ost(ML) July 2014
|
||||
-- "magic" constants converted to vhdl types
|
||||
-- Ver 300 Bugfixes by ehenciak added
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
-- See list of changes in T65 top file (T65.vhd)...
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- 65xx compatible microprocessor core
|
||||
--
|
||||
-- Version : 0246
|
||||
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
-- Copyright (c) 2002...2015
|
||||
-- Daniel Wallner (jesus <at> opencores <dot> org)
|
||||
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
|
||||
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
|
||||
-- Morten Leikvoll ()
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
|
@ -44,17 +42,12 @@
|
|||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- Please report bugs to the author(s), but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t65/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- See in T65 top file (T65.vhd)...
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
@ -70,6 +63,18 @@ package T65_Pack is
|
|||
constant Flag_V : integer := 6;
|
||||
constant Flag_N : integer := 7;
|
||||
|
||||
subtype T_Lcycle is std_logic_vector(2 downto 0);
|
||||
constant Cycle_sync :T_Lcycle:="000";
|
||||
constant Cycle_1 :T_Lcycle:="001";
|
||||
constant Cycle_2 :T_Lcycle:="010";
|
||||
constant Cycle_3 :T_Lcycle:="011";
|
||||
constant Cycle_4 :T_Lcycle:="100";
|
||||
constant Cycle_5 :T_Lcycle:="101";
|
||||
constant Cycle_6 :T_Lcycle:="110";
|
||||
constant Cycle_7 :T_Lcycle:="111";
|
||||
|
||||
function CycleNext(c:T_Lcycle) return T_Lcycle;
|
||||
|
||||
type T_Set_BusA_To is
|
||||
(
|
||||
Set_BusA_To_DI,
|
||||
|
@ -78,15 +83,21 @@ package T65_Pack is
|
|||
Set_BusA_To_Y,
|
||||
Set_BusA_To_S,
|
||||
Set_BusA_To_P,
|
||||
Set_BusA_To_DA,
|
||||
Set_BusA_To_DAO,
|
||||
Set_BusA_To_DAX,
|
||||
Set_BusA_To_AAX,
|
||||
Set_BusA_To_DONTCARE
|
||||
);
|
||||
|
||||
type T_Set_Addr_To is
|
||||
(
|
||||
Set_Addr_To_S,
|
||||
Set_Addr_To_AD,
|
||||
Set_Addr_To_PBR,
|
||||
Set_Addr_To_SP,
|
||||
Set_Addr_To_ZPG,
|
||||
Set_Addr_To_BA
|
||||
);
|
||||
|
||||
type T_Write_Data is
|
||||
(
|
||||
Write_Data_DL,
|
||||
|
@ -97,74 +108,73 @@ package T65_Pack is
|
|||
Write_Data_P,
|
||||
Write_Data_PCL,
|
||||
Write_Data_PCH,
|
||||
Write_Data_AX,
|
||||
Write_Data_AXB,
|
||||
Write_Data_XB,
|
||||
Write_Data_YB,
|
||||
Write_Data_DONTCARE
|
||||
);
|
||||
|
||||
type T_ALU_OP is
|
||||
(
|
||||
ALU_OP_OR, --"0000"
|
||||
ALU_OP_AND, --"0001"
|
||||
ALU_OP_EOR, --"0010"
|
||||
ALU_OP_ADC, --"0011"
|
||||
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
|
||||
ALU_OP_EQ2, --"0101"Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
|
||||
ALU_OP_CMP, --"0110"
|
||||
ALU_OP_SBC, --"0111"
|
||||
ALU_OP_ASL, --"1000"
|
||||
ALU_OP_ROL, --"1001"
|
||||
ALU_OP_LSR, --"1010"
|
||||
ALU_OP_ROR, --"1011"
|
||||
ALU_OP_BIT, --"1100"
|
||||
ALU_OP_EQ3, --"1101"
|
||||
ALU_OP_DEC, --"1110"
|
||||
ALU_OP_INC, --"1111"
|
||||
ALU_OP_UNDEF--"----"--may be replaced with any?
|
||||
ALU_OP_OR, --"0000"
|
||||
ALU_OP_AND, --"0001"
|
||||
ALU_OP_EOR, --"0010"
|
||||
ALU_OP_ADC, --"0011"
|
||||
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
|
||||
ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
|
||||
ALU_OP_CMP, --"0110"
|
||||
ALU_OP_SBC, --"0111"
|
||||
ALU_OP_ASL, --"1000"
|
||||
ALU_OP_ROL, --"1001"
|
||||
ALU_OP_LSR, --"1010"
|
||||
ALU_OP_ROR, --"1011"
|
||||
ALU_OP_BIT, --"1100"
|
||||
-- ALU_OP_EQ3, --"1101"
|
||||
ALU_OP_DEC, --"1110"
|
||||
ALU_OP_INC, --"1111"
|
||||
ALU_OP_ARR,
|
||||
ALU_OP_ANC,
|
||||
ALU_OP_SAX,
|
||||
ALU_OP_XAA
|
||||
-- ALU_OP_UNDEF--"----"--may be replaced with any?
|
||||
);
|
||||
|
||||
component T65_MCode
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
P : in std_logic_vector(7 downto 0);
|
||||
LCycle : out std_logic_vector(2 downto 0);
|
||||
ALU_Op : out T_ALU_Op;
|
||||
Set_BusA_To : out T_Set_BusA_To;-- DI,A,X,Y,S,P
|
||||
Set_Addr_To : out T_Set_Addr_To;-- PC Adder,S,AD,BA
|
||||
Write_Data : out T_Write_Data;-- DL,A,X,Y,S,P,PCL,PCH
|
||||
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
|
||||
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
|
||||
BreakAtNA : out std_logic;
|
||||
ADAdd : out std_logic;
|
||||
AddY : out std_logic;
|
||||
PCAdd : out std_logic;
|
||||
Inc_S : out std_logic;
|
||||
Dec_S : out std_logic;
|
||||
LDA : out std_logic;
|
||||
LDP : out std_logic;
|
||||
LDX : out std_logic;
|
||||
LDY : out std_logic;
|
||||
LDS : out std_logic;
|
||||
LDDI : out std_logic;
|
||||
LDALU : out std_logic;
|
||||
LDAD : out std_logic;
|
||||
LDBAL : out std_logic;
|
||||
LDBAH : out std_logic;
|
||||
SaveP : out std_logic;
|
||||
ALUmore : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T65_ALU
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
|
||||
Op : in T_ALU_Op;
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
P_In : in std_logic_vector(7 downto 0);
|
||||
P_Out : out std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
type T_t65_dbg is record
|
||||
I : std_logic_vector(7 downto 0); -- instruction
|
||||
A : std_logic_vector(7 downto 0); -- A reg
|
||||
X : std_logic_vector(7 downto 0); -- X reg
|
||||
Y : std_logic_vector(7 downto 0); -- Y reg
|
||||
S : std_logic_vector(7 downto 0); -- stack pointer
|
||||
P : std_logic_vector(7 downto 0); -- processor flags
|
||||
end record;
|
||||
|
||||
end;
|
||||
|
||||
package body T65_Pack is
|
||||
|
||||
function CycleNext(c:T_Lcycle) return T_Lcycle is
|
||||
begin
|
||||
case(c) is
|
||||
when Cycle_sync=>
|
||||
return Cycle_1;
|
||||
when Cycle_1=>
|
||||
return Cycle_2;
|
||||
when Cycle_2=>
|
||||
return Cycle_3;
|
||||
when Cycle_3=>
|
||||
return Cycle_4;
|
||||
when Cycle_4=>
|
||||
return Cycle_5;
|
||||
when Cycle_5=>
|
||||
return Cycle_6;
|
||||
when Cycle_6=>
|
||||
return Cycle_7;
|
||||
when Cycle_7=>
|
||||
return Cycle_sync;
|
||||
when others=>
|
||||
return Cycle_sync;
|
||||
end case;
|
||||
end CycleNext;
|
||||
|
||||
end T65_Pack;
|
||||
|
|
Loading…
Reference in New Issue