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z80: added a resume state

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This allows time for the paused instruction to be re-read

Without this, the Acorn Z80 Co Pro always seemed to be single
stepping NOP instructions.

Change-Id: I0bcb424293071efc0370b862854455a33f42faf2
This commit is contained in:
David Banks 2019-10-15 11:46:50 +01:00
parent 9bcea56588
commit 5845409961
1 changed files with 13 additions and 9 deletions
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22
src/Z80CpuMon.vhd
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@ -84,7 +84,7 @@ end Z80CpuMon;
architecture behavioral of Z80CpuMon is architecture behavioral of Z80CpuMon is
type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3); type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3);
signal state : state_type; signal state : state_type;
@ -386,14 +386,14 @@ begin
-- TODO: Also need to take account of BUSRQ_n/BUSAK_n -- TODO: Also need to take account of BUSRQ_n/BUSAK_n
MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n; MREQ_n <= MREQ_n_int when state = idle or state = resume else mon_mreq_n;
IORQ_n <= IORQ_n_int when state = idle else mon_iorq_n; IORQ_n <= IORQ_n_int when state = idle or state = resume else mon_iorq_n;
RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n; RFSH_n <= RFSH_n_int when state = idle or state = resume else mon_rfsh_n;
WR_n <= WR_n_int when state = idle else mon_wr_n; WR_n <= WR_n_int when state = idle or state = resume else mon_wr_n;
RD_n <= RD_n_int when state = idle else mon_rd_n; RD_n <= RD_n_int when state = idle or state = resume else mon_rd_n;
M1_n <= M1_n_int when state = idle else '1'; M1_n <= M1_n_int when state = idle or state = resume else '1';
Addr <= Addr_int when state = idle else Addr <= Addr_int when state = idle or state = resume else
x"0000" when state = nop_t1 or state = nop_t2 else x"0000" when state = nop_t1 or state = nop_t2 else
rfsh_addr when state = nop_t3 or state = nop_t4 else rfsh_addr when state = nop_t3 or state = nop_t4 else
memory_addr; memory_addr;
@ -482,11 +482,15 @@ begin
state <= rd_t1; state <= rd_t1;
io_not_mem <= io_rd1; io_not_mem <= io_rd1;
elsif SS_Step_held = '1' or SS_Single = '0' then elsif SS_Step_held = '1' or SS_Single = '0' then
state <= idle; state <= resume;
else else
state <= nop_t1; state <= nop_t1;
end if; end if;
-- Resume,
when resume =>
state <= idle;
-- Read cycle -- Read cycle
when rd_t1 => when rd_t1 =>
if io_not_mem = '1' then if io_not_mem = '1' then