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On LX9 board, updated Tx=51 and Rx=55

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Change-Id: I5bcd032eab29ef93d36e8011fee673028042483f
This commit is contained in:
David Banks 2017-07-29 19:55:27 +01:00
parent f84780b304
commit 6415a81a40
18 changed files with 97 additions and 37 deletions
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11
src/DCM/DCM0.vhd
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@ -5,6 +5,11 @@ library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
generic (
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
);
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end DCM0;
@ -23,10 +28,10 @@ begin
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 15.855 =49.152 * 10 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 10,
CLKFX_DIVIDE => ClkDiv,
CLKFX_MULTIPLY => ClkMult,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.345,
CLKIN_PERIOD => ClkPer,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",

56
src/Z80CpuMon.vhd
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@ -26,7 +26,10 @@ entity Z80CpuMon is
UseT80Core : boolean := true;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL
SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
);
port (
clock49 : in std_logic;
@ -150,6 +153,11 @@ type state_type is (idle, rd_init, rd_setup, rd, rd_hold, wr_init, wr_setup, wr,
signal sw_interrupt_n : std_logic; -- switch to pause the CPU
signal sw_reset_n : std_logic; -- switch to reset the CPU
signal avr_TxD_int : std_logic;
signal clock_49_ctr : std_logic_vector(23 downto 0);
signal clock_avr_ctr : std_logic_vector(23 downto 0);
begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
@ -159,10 +167,16 @@ begin
led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore
generic map (
@ -192,7 +206,7 @@ begin
lcd_e => open,
lcd_db => open,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
avr_TxD => avr_TxD_int,
sw1 => '0',
nsw2 => sw_interrupt_n,
led3 => led3_n,
@ -402,10 +416,32 @@ begin
RESET_n_int <= RESET_n and sw_reset_n and nRST;
test1 <= TState(0);
test2 <= TState(1);
test3 <= TState(2);
test4 <= CLK_n;
avr_TxD <= avr_Txd_int;
test1 <= sw_reset_n and sw_interrupt_n;
process(clock_avr)
begin
if rising_edge(clock_avr) then
clock_avr_ctr <= clock_avr_ctr + 1;
test2 <= sw_reset_n or clock_avr_ctr(23);
end if;
end process;
process(clock49)
begin
if rising_edge(clock49) then
clock_49_ctr <= clock_49_ctr + 1;
test3 <= sw_interrupt_n or clock_49_ctr(23);
end if;
end process;
test4 <= not avr_TxD_int;
--test1 <= TState(0);
--test2 <= TState(1);
--test3 <= TState(2);
--test4 <= CLK_n;
cpu_clk <= CLK_n;
busmon_clk <= CLK_n;

4
target/common/Makefile.inc
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@ -5,12 +5,14 @@ XILINX ?= /opt/Xilinx/14.7
PATH := $(PATH):${XILINX}/ISE_DS/ISE/bin/lin:${PAPILIO}/linux32
SHELL := env PATH=$(PATH) /bin/bash
# Frequency of the AVR CPU
F_CPU ?= 15855484
# Path of the back anotated block memory map file
BMM_FILE ?= memory_bd.bmm
# AVR dev environment
MCU=atmega103
F_CPU=15855484
CC=avr-gcc
OBJCOPY=avr-objcopy

3
target/lx9_jason/ice6502/Makefile
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@ -10,6 +10,9 @@ PROJECT = AtomCpuMon
# The target .bit file to be generated including the monitor program
TARGET = ice6502
# Frequuency that the AVR runs at
F_CPU = 19354838
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

4
target/lx9_jason/ice6502/board.ucf
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@ -63,8 +63,8 @@ NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P47" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;

2
target/lx9_jason/ice6502/ice6502.xise
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@ -370,7 +370,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

3
target/lx9_jason/ice6502fast/Makefile
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@ -10,6 +10,9 @@ PROJECT = AtomFast6502
# The target .bit file to be generated including the monitor program
TARGET = ice6502fast
# Frequuency that the AVR runs at
F_CPU = 19354838
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

4
target/lx9_jason/ice6502fast/board.ucf
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@ -63,8 +63,8 @@ NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P47" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;

2
target/lx9_jason/ice6502fast/ice6502fast.xise
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@ -374,7 +374,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

3
target/lx9_jason/ice6502mon/Makefile
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@ -10,6 +10,9 @@ PROJECT = AtomBusMon
# The target .bit file to be generated including the monitor program
TARGET = ice6502mon
# Frequuency that the AVR runs at
F_CPU = 19354838
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

4
target/lx9_jason/ice6502mon/board.ucf
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@ -63,8 +63,8 @@ NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P47" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;

2
target/lx9_jason/ice6502mon/ice6502mon.xise
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@ -342,7 +342,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=31 ClkDiv=12 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

3
target/lx9_jason/ice6809/Makefile
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@ -10,6 +10,9 @@ PROJECT = MC6809ECpuMon
# The target .bit file to be generated including the monitor program
TARGET = ice6809
# Frequuency that the AVR runs at
F_CPU = 19354838
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

13
target/lx9_jason/ice6809/board.ucf
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@ -62,18 +62,19 @@ NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P47" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
# Test outputs
NET "test1" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test2" LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test3" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test4" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test1" LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led1
NET "test2" LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led2
#NET "test3" LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led4
#NET "test4" LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led5
#NET "test5" LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led7
# A clock generated from the 50.000MHz clock
NET "clock_test" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

2
target/lx9_jason/ice6809/ice6809.xise
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@ -354,7 +354,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

3
target/lx9_jason/icez80/Makefile
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@ -10,6 +10,9 @@ PROJECT = Z80CpuMon
# The target .bit file to be generated including the monitor program
TARGET = icez80
# Frequuency that the AVR runs at
F_CPU = 19354838
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

13
target/lx9_jason/icez80/board.ucf
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@ -61,15 +61,16 @@ NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P47" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
# Test outputs
NET "test1" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test2" LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test3" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test4" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test1" LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led1
NET "test2" LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led2
NET "test3" LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led4
NET "test4" LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led5
#NET "test5" LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led7

2
target/lx9_jason/icez80/icez80.xise
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@ -370,7 +370,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>