diff --git a/src/BusMonCore.vhd b/src/BusMonCore.vhd index a4dcacb..8508dfb 100644 --- a/src/BusMonCore.vhd +++ b/src/BusMonCore.vhd @@ -102,7 +102,15 @@ end BusMonCore; architecture behavioral of BusMonCore is + + signal cpu_reset_n : std_logic; signal nrst_avr : std_logic; + signal nrst1 : std_logic; + signal nrst2 : std_logic; + signal nrst3 : std_logic; + + -- debounce time is 2^17 / 16MHz = 8.192ms + signal nrst_counter : unsigned(17 downto 0); signal dy_counter : std_logic_vector(31 downto 0); signal dy_data : y2d_type ; @@ -162,6 +170,8 @@ architecture behavioral of BusMonCore is signal last_done : std_logic; signal inc_addr : std_logic; + signal reset_counter : std_logic_vector(9 downto 0); + begin inst_oho_dy1 : entity work.Oho_Dy1 port map ( @@ -216,7 +226,7 @@ begin portdin(3) => '0', portdin(4) => '0', portdin(5) => '0', - portdin(6) => sw_interrupt, + portdin(6) => '0', -- sw_interrupt, portdin(7) => fifo_empty_n, portdout(0) => muxsel(0), @@ -408,7 +418,7 @@ begin if rising_edge(busmon_clk) then if busmon_clken = '1' then -- Cycle counter, wraps every 16s at 1MHz - if (nRSTin = '0') then + if (cpu_reset_n = '0') then cycleCount <= (others => '0'); elsif (CountCycle = '1') then cycleCount <= cycleCount + 1; @@ -493,8 +503,6 @@ begin Rdy_int <= (not Sync); end if; - nRSTout <= not reset; - -- Latch instruction address for the whole cycle if (Sync = '1') then addr_inst <= Addr; @@ -542,4 +550,51 @@ begin DataOut <= addr_dout_reg(7 downto 0); SS_Single <= single; + -- Reset Logic + -- Generate a short (~1ms @ 1MHz) power up reset pulse + -- + -- This is in case FPGA configuration takes longer than + -- the length of the host system reset pulse. + -- + -- Some 6502 cores (particularly the AlanD core) needs + -- reset to be asserted to start. + + + + -- Debounce nRSTin using clock_avr as this is always 16MHz + -- nrst1 is the possibly glitchy input + -- nrst2 is the filtered output + process(clock_avr) + begin + if rising_edge(clock_avr) then + -- Syncronise nRSTin + nrst1 <= nRSTin and (not sw_interrupt); + -- De-glitch NRST + if nrst1 = '0' then + nrst_counter <= to_unsigned(0, nrst_counter'length); + nrst2 <= '0'; + elsif nrst_counter(nrst_counter'high) = '0' then + nrst_counter <= nrst_counter + 1; + else + nrst2 <= '1'; + end if; + end if; + end process; + + + process(cpu_clk) + begin + if rising_edge(cpu_clk) then + if cpu_clken = '1' then + if reset_counter(reset_counter'high) = '0' then + reset_counter <= reset_counter + 1; + end if; + nrst3 <= nrst2; + cpu_reset_n <= nrst3 and reset_counter(reset_counter'high) and (not reset); + end if; + end if; + end process; + + nRSTout <= cpu_reset_n; + end behavioral; diff --git a/src/MC6809CpuMon.vhd b/src/MC6809CpuMon.vhd index 7f0049f..8744dee 100644 --- a/src/MC6809CpuMon.vhd +++ b/src/MC6809CpuMon.vhd @@ -92,12 +92,12 @@ architecture behavioral of MC6809CpuMon is signal clock_avr : std_logic; signal cpu_clk : std_logic; + signal cpu_reset_n : std_logic; signal busmon_clk : std_logic; signal R_W_n_int : std_logic; signal NMI_sync : std_logic; signal IRQ_sync : std_logic; signal FIRQ_sync : std_logic; - signal nRST_sync : std_logic; signal HALT_sync : std_logic; signal Addr_int : std_logic_vector(15 downto 0); signal Din : std_logic_vector(7 downto 0); @@ -184,8 +184,8 @@ begin WrIO_n => '1', Sync => Sync_int, Rdy => open, - nRSTin => nRST_sync, - nRSTout => nRSTout, + nRSTin => RES_n, + nRSTout => cpu_reset_n, CountCycle => CountCycle, trig => trig, avr_RxD => avr_RxD, @@ -244,7 +244,7 @@ begin inst_cpu09: entity work.cpu09 port map ( clk => cpu_clk, - rst => not nRST_sync, + rst => not cpu_reset_n, vma => AVMA, lic_out => LIC_int, ifetch => ifetch, @@ -271,7 +271,6 @@ begin NMI_sync <= not NMI_n_masked; IRQ_sync <= not IRQ_n_masked; FIRQ_sync <= not FIRQ_n_masked; - nRST_sync <= RES_n and nRSTout; HALT_sync <= not HALT_n; end if; end process; diff --git a/src/MOS6502CpuMonCore.vhd b/src/MOS6502CpuMonCore.vhd index 14ffc34..314c0af 100644 --- a/src/MOS6502CpuMonCore.vhd +++ b/src/MOS6502CpuMonCore.vhd @@ -85,12 +85,10 @@ architecture behavioral of MOS6502CpuMonCore is signal Wr_n_int : std_logic; signal Sync_int : std_logic; signal Addr_int : std_logic_vector(23 downto 0); - signal Res_n_out : std_logic; signal cpu_addr_us : unsigned (15 downto 0); signal cpu_dout_us : unsigned (7 downto 0); signal cpu_reset_n : std_logic; - signal reset_counter : std_logic_vector(9 downto 0); signal Regs : std_logic_vector(63 downto 0); signal Regs1 : std_logic_vector(255 downto 0); @@ -135,7 +133,7 @@ begin Sync => Sync_int, Rdy => open, nRSTin => Res_n, - nRSTout => Res_n_out, + nRSTout => cpu_reset_n, CountCycle => CountCycle, trig => trig, avr_RxD => avr_RxD, @@ -196,24 +194,6 @@ begin cpu_clken_ss <= '1' when Rdy = '1' and (state = idle) and cpu_clken = '1' else '0'; - -- Generate a short (~1ms @ 1MHz) power up reset pulse - -- - -- This is in case FPGA configuration takes longer than - -- the length of the host system reset pulse. - -- - -- Some 6502 cores (particularly the AlanD core) needs - -- reset to be asserted to start. - - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if reset_counter(reset_counter'high) = '0' then - reset_counter <= reset_counter + 1; - end if; - cpu_reset_n <= Res_n and Res_n_out and reset_counter(reset_counter'high); - end if; - end process; - GenT65Core: if UseT65Core generate inst_t65: entity work.T65 port map ( mode => "00", diff --git a/src/Z80CpuMon.vhd b/src/Z80CpuMon.vhd index 95e8b17..5232045 100644 --- a/src/Z80CpuMon.vhd +++ b/src/Z80CpuMon.vhd @@ -94,7 +94,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r signal clock_avr : std_logic; - signal RESET_n_int : std_logic; + signal cpu_reset_n : std_logic; signal cpu_clk : std_logic; signal cpu_clken : std_logic; signal busmon_clk : std_logic; @@ -225,8 +225,8 @@ begin WrIO_n => WriteIO_n, Sync => Sync, Rdy => open, - nRSTin => RESET_n_int, - nRSTout => nRST, + nRSTin => RESET_n, + nRSTout => cpu_reset_n, CountCycle => CountCycle, trig => trig, avr_RxD => avr_RxD, @@ -262,7 +262,7 @@ begin TS => TState, Regs => Regs, PdcData => PdcData, - RESET_n => RESET_n_int, + RESET_n => cpu_reset_n, CLK_n => cpu_clk, CEN => cpu_clken, WAIT_n => WAIT_n, @@ -444,9 +444,9 @@ begin Din <= Data; - men_access_machine_rising : process(CLK_n, RESET_n) + men_access_machine_rising : process(CLK_n, cpu_reset_n) begin - if (RESET_n = '0') then + if (cpu_reset_n = '0') then state <= idle; memory_rd1 <= '0'; memory_wr1 <= '0'; @@ -644,8 +644,6 @@ begin mon_busak_n <= mon_busak_n1 or mon_busak_n2; - RESET_n_int <= RESET_n and (not sw_interrupt) and nRST; - avr_TxD <= avr_Txd_int; test1 <= Sync1;