diff --git a/src/Z80CpuMon.vhd b/src/Z80CpuMon.vhd index 325067b..5537608 100644 --- a/src/Z80CpuMon.vhd +++ b/src/Z80CpuMon.vhd @@ -52,6 +52,7 @@ entity Z80CpuMon is -- Buffer Control Signals DIRD : out std_logic; tristate_n : out std_logic; + tristate_ad_n : out std_logic; -- Mode jumper, tie low to generate NOPs when paused mode : in std_logic; @@ -415,6 +416,11 @@ begin BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n; + -- Force the address and databus to tristate when reset is asserted + tristate_ad_n <= '0' when RESET_n = '0' else + BUSAK_n_int when state = idle else + mon_busak_n1; + -- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1 -- and MREQ being released at the start of T3. Otherwise, the ROM switching -- during NMI doesn't work reliably due to glitches. See: diff --git a/src/Z80CpuMonALS.vhd b/src/Z80CpuMonALS.vhd index 8996238..b19bfba 100644 --- a/src/Z80CpuMonALS.vhd +++ b/src/Z80CpuMonALS.vhd @@ -95,6 +95,7 @@ architecture behavioral of Z80CpuMonALS is signal HALT_n_int : std_logic; signal BUSAK_n_int : std_logic; signal tristate_n : std_logic; + signal tristate_ad_n: std_logic; signal sw_reset_cpu : std_logic; signal sw_reset_avr : std_logic; @@ -121,9 +122,9 @@ begin BUSAK_n <= BUSAK_n_int; OEC_n <= not tristate_n; - OEA1_n <= not tristate_n; - OEA2_n <= not tristate_n; - OED_n <= not tristate_n; + OEA1_n <= not tristate_ad_n; + OEA2_n <= not tristate_ad_n; + OED_n <= not tristate_ad_n; wrapper : entity work.Z80CpuMon generic map ( @@ -157,6 +158,7 @@ begin -- Buffer Control Signals DIRD => DIRD, tristate_n => tristate_n, + tristate_ad_n => tristate_ad_n, -- Mode jumper, tie low to generate NOPs when paused mode => mode, diff --git a/src/Z80CpuMonGODIL.vhd b/src/Z80CpuMonGODIL.vhd index 39410b4..c8d02a7 100644 --- a/src/Z80CpuMonGODIL.vhd +++ b/src/Z80CpuMonGODIL.vhd @@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonGODIL is signal Addr_int : std_logic_vector(15 downto 0); signal tristate_n : std_logic; + signal tristate_ad_n: std_logic; begin sw_reset_cpu <= sw1; @@ -107,7 +108,7 @@ begin IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int; RD_n <= 'Z' when tristate_n = '0' else RD_n_int; WR_n <= 'Z' when tristate_n = '0' else WR_n_int; - Addr <= (others => 'Z') when tristate_n = '0' else Addr_int; + Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int; wrapper : entity work.Z80CpuMon generic map ( @@ -140,6 +141,7 @@ begin -- Buffer Control Signals tristate_n => tristate_n, + tristate_ad_n => tristate_ad_n, DIRD => open, -- Mode jumper, tie low to generate NOPs when paused diff --git a/src/Z80CpuMonLX9.vhd b/src/Z80CpuMonLX9.vhd index 5e6d9c0..9dd05d3 100644 --- a/src/Z80CpuMonLX9.vhd +++ b/src/Z80CpuMonLX9.vhd @@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonLX9 is signal Addr_int : std_logic_vector(15 downto 0); signal tristate_n : std_logic; + signal tristate_ad_n: std_logic; begin @@ -108,7 +109,7 @@ begin IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int; RD_n <= 'Z' when tristate_n = '0' else RD_n_int; WR_n <= 'Z' when tristate_n = '0' else WR_n_int; - Addr <= (others => 'Z') when tristate_n = '0' else Addr_int; + Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int; wrapper : entity work.Z80CpuMon generic map ( @@ -141,6 +142,7 @@ begin -- Buffer Control Signals tristate_n => tristate_n, + tristate_ad_n => tristate_ad_n, DIRD => open, -- Mode jumper, tie low to generate NOPs when paused