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Z80: tristate A and D when reset asserted
Change-Id: Ieeb558b5df1a7b3705874468c98a0b72ebb2d505
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@ -52,6 +52,7 @@ entity Z80CpuMon is
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-- Buffer Control Signals
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-- Buffer Control Signals
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DIRD : out std_logic;
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DIRD : out std_logic;
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tristate_n : out std_logic;
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tristate_n : out std_logic;
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tristate_ad_n : out std_logic;
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-- Mode jumper, tie low to generate NOPs when paused
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-- Mode jumper, tie low to generate NOPs when paused
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mode : in std_logic;
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mode : in std_logic;
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@ -415,6 +416,11 @@ begin
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BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
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BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
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-- Force the address and databus to tristate when reset is asserted
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tristate_ad_n <= '0' when RESET_n = '0' else
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BUSAK_n_int when state = idle else
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mon_busak_n1;
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-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
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-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
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-- and MREQ being released at the start of T3. Otherwise, the ROM switching
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-- and MREQ being released at the start of T3. Otherwise, the ROM switching
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-- during NMI doesn't work reliably due to glitches. See:
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-- during NMI doesn't work reliably due to glitches. See:
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@ -95,6 +95,7 @@ architecture behavioral of Z80CpuMonALS is
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signal HALT_n_int : std_logic;
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signal HALT_n_int : std_logic;
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signal BUSAK_n_int : std_logic;
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signal BUSAK_n_int : std_logic;
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signal tristate_n : std_logic;
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signal tristate_n : std_logic;
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signal tristate_ad_n: std_logic;
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signal sw_reset_cpu : std_logic;
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signal sw_reset_cpu : std_logic;
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signal sw_reset_avr : std_logic;
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signal sw_reset_avr : std_logic;
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@ -121,9 +122,9 @@ begin
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BUSAK_n <= BUSAK_n_int;
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BUSAK_n <= BUSAK_n_int;
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OEC_n <= not tristate_n;
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OEC_n <= not tristate_n;
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OEA1_n <= not tristate_n;
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OEA1_n <= not tristate_ad_n;
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OEA2_n <= not tristate_n;
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OEA2_n <= not tristate_ad_n;
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OED_n <= not tristate_n;
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OED_n <= not tristate_ad_n;
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wrapper : entity work.Z80CpuMon
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wrapper : entity work.Z80CpuMon
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generic map (
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generic map (
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@ -157,6 +158,7 @@ begin
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-- Buffer Control Signals
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-- Buffer Control Signals
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DIRD => DIRD,
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DIRD => DIRD,
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tristate_n => tristate_n,
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tristate_n => tristate_n,
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tristate_ad_n => tristate_ad_n,
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-- Mode jumper, tie low to generate NOPs when paused
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-- Mode jumper, tie low to generate NOPs when paused
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mode => mode,
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mode => mode,
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@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonGODIL is
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Addr_int : std_logic_vector(15 downto 0);
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signal tristate_n : std_logic;
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signal tristate_n : std_logic;
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signal tristate_ad_n: std_logic;
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begin
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begin
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sw_reset_cpu <= sw1;
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sw_reset_cpu <= sw1;
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@ -107,7 +108,7 @@ begin
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IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
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IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
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RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
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RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
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WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
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WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
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Addr <= (others => 'Z') when tristate_n = '0' else Addr_int;
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Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
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wrapper : entity work.Z80CpuMon
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wrapper : entity work.Z80CpuMon
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generic map (
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generic map (
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@ -140,6 +141,7 @@ begin
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-- Buffer Control Signals
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-- Buffer Control Signals
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tristate_n => tristate_n,
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tristate_n => tristate_n,
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tristate_ad_n => tristate_ad_n,
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DIRD => open,
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DIRD => open,
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-- Mode jumper, tie low to generate NOPs when paused
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-- Mode jumper, tie low to generate NOPs when paused
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@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonLX9 is
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Addr_int : std_logic_vector(15 downto 0);
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signal tristate_n : std_logic;
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signal tristate_n : std_logic;
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signal tristate_ad_n: std_logic;
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begin
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begin
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@ -108,7 +109,7 @@ begin
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IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
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IORQ_n <= 'Z' when tristate_n = '0' else IORQ_n_int;
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RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
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RD_n <= 'Z' when tristate_n = '0' else RD_n_int;
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WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
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WR_n <= 'Z' when tristate_n = '0' else WR_n_int;
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Addr <= (others => 'Z') when tristate_n = '0' else Addr_int;
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Addr <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
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wrapper : entity work.Z80CpuMon
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wrapper : entity work.Z80CpuMon
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generic map (
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generic map (
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@ -141,6 +142,7 @@ begin
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-- Buffer Control Signals
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-- Buffer Control Signals
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tristate_n => tristate_n,
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tristate_n => tristate_n,
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tristate_ad_n => tristate_ad_n,
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DIRD => open,
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DIRD => open,
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-- Mode jumper, tie low to generate NOPs when paused
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-- Mode jumper, tie low to generate NOPs when paused
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