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Refactor: 2nd stage - bug fixes

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Change-Id: Ic3bd520d0cc8b74f33068c53085229506d6968b2
This commit is contained in:
David Banks 2015-10-31 18:31:41 +00:00
parent 99c5f951d1
commit 6aeb0c7b8a
3 changed files with 66 additions and 51 deletions
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2
firmware/AtomBusMon.c
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@ -10,7 +10,7 @@
* VERSION and NAME are used in the start-up message * VERSION and NAME are used in the start-up message
********************************************************/ ********************************************************/
#define VERSION "0.66" #define VERSION "0.70"
#if (CPU == Z80) #if (CPU == Z80)
#define NAME "ICE-T80" #define NAME "ICE-T80"

10
src/AtomCpuMon.vhd
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@ -99,7 +99,12 @@ begin
CLK2X_OUT => open CLK2X_OUT => open
); );
core : entity work.MOS6502CpuMonCore port map( core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore
)
port map (
clock_avr => clock_avr, clock_avr => clock_avr,
busmon_clk => busmon_clk, busmon_clk => busmon_clk,
busmon_clken => '1', busmon_clken => '1',
@ -113,7 +118,8 @@ begin
Din => Din, Din => Din,
Dout => Dout, Dout => Dout,
SO_n => SO_n, SO_n => SO_n,
Res_n => Res_n, Res_n_in => Res_n,
Res_n_out => Res_n,
Rdy => Rdy, Rdy => Rdy,
trig => trig, trig => trig,
avr_RxD => avr_RxD, avr_RxD => avr_RxD,

33
src/MOS6502CpuMonCore.vhd
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@ -21,11 +21,10 @@ use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.OhoPack.all ; use work.OhoPack.all ;
entity MOS6502CpuMonCore is entity MOS6502CpuMonCore is
generic ( generic (
UseT65Core : boolean := true; UseT65Core : boolean;
UseAlanDCore : boolean := false UseAlanDCore : boolean
); );
port ( port (
clock_avr : in std_logic; clock_avr : in std_logic;
@ -44,7 +43,8 @@ entity MOS6502CpuMonCore is
Din : in std_logic_vector(7 downto 0); Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0); Dout : out std_logic_vector(7 downto 0);
SO_n : in std_logic; SO_n : in std_logic;
Res_n : inout std_logic; Res_n_in : in std_logic;
Res_n_out : out std_logic;
Rdy : in std_logic; Rdy : in std_logic;
-- External trigger inputs -- External trigger inputs
@ -72,6 +72,7 @@ end MOS6502CpuMonCore;
architecture behavioral of MOS6502CpuMonCore is architecture behavioral of MOS6502CpuMonCore is
signal cpu_clken_ss : std_logic;
signal Data : std_logic_vector(7 downto 0); signal Data : std_logic_vector(7 downto 0);
signal Dout_int : std_logic_vector(7 downto 0); signal Dout_int : std_logic_vector(7 downto 0);
signal R_W_n_int : std_logic; signal R_W_n_int : std_logic;
@ -106,9 +107,9 @@ begin
mon : entity work.BusMonCore port map ( mon : entity work.BusMonCore port map (
clock_avr => clock_avr, clock_avr => clock_avr,
busmon_clk => busmon_clk, busmon_clk => busmon_clk,
busmon_clken => '1', busmon_clken => busmon_clken,
cpu_clk => cpu_clk, cpu_clk => cpu_clk,
cpu_clken => '1', cpu_clken => cpu_clken,
Addr => Addr_int, Addr => Addr_int,
Data => Data, Data => Data,
Rd_n => not R_W_n_int, Rd_n => not R_W_n_int,
@ -117,8 +118,8 @@ begin
WrIO_n => '1', WrIO_n => '1',
Sync => Sync_int, Sync => Sync_int,
Rdy => open, Rdy => open,
nRSTin => Res_n, nRSTin => Res_n_in,
nRSTout => Res_n, nRSTout => Res_n_out,
CountCycle => CountCycle, CountCycle => CountCycle,
trig => trig, trig => trig,
lcd_rs => open, lcd_rs => open,
@ -164,23 +165,27 @@ begin
last_pc_gen : process(cpu_clk) last_pc_gen : process(cpu_clk)
begin begin
if rising_edge(cpu_clk) then if rising_edge(cpu_clk) then
if (cpu_clken = '1') then
if (hold = '0') then if (hold = '0') then
last_PC <= Regs(63 downto 48); last_PC <= Regs(63 downto 48);
end if; end if;
end if; end if;
end if;
end process; end process;
Regs1( 47 downto 0) <= Regs( 47 downto 0); Regs1( 47 downto 0) <= Regs( 47 downto 0);
Regs1( 63 downto 48) <= last_PC; Regs1( 63 downto 48) <= last_PC;
Regs1(255 downto 64) <= (others => '0'); Regs1(255 downto 64) <= (others => '0');
cpu_clken_ss <= (not hold) and cpu_clken;
GenT65Core: if UseT65Core generate GenT65Core: if UseT65Core generate
inst_t65: entity work.T65 port map ( inst_t65: entity work.T65 port map (
mode => "00", mode => "00",
Abort_n => '1', Abort_n => '1',
SO_n => SO_n, SO_n => SO_n,
Res_n => Res_n, Res_n => Res_n_in,
Enable => not hold, Enable => cpu_clken_ss,
Clk => cpu_clk, Clk => cpu_clk,
Rdy => '1', Rdy => '1',
IRQ_n => IRQ_n, IRQ_n => IRQ_n,
@ -197,9 +202,9 @@ begin
GenAlanDCore: if UseAlanDCore generate GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map ( inst_r65c02: entity work.r65c02 port map (
reset => RES_n, reset => Res_n_in,
clk => cpu_clk, clk => cpu_clk,
enable => not hold, enable => cpu_clken_ss,
nmi_n => NMI_n, nmi_n => NMI_n,
irq_n => IRQ_n, irq_n => IRQ_n,
di => unsigned(Din), di => unsigned(Din),
@ -220,6 +225,7 @@ begin
hold_gen : process(cpu_clk) hold_gen : process(cpu_clk)
begin begin
if rising_edge(cpu_clk) then if rising_edge(cpu_clk) then
if (cpu_clken = '1') then
if (Sync_int = '1') then if (Sync_int = '1') then
-- stop after the opcode has been fetched -- stop after the opcode has been fetched
hold <= SS_Single; hold <= SS_Single;
@ -228,6 +234,7 @@ begin
hold <= '0'; hold <= '0';
end if; end if;
end if; end if;
end if;
end process; end process;
-- Only count cycles when the 6809 is actually running -- Only count cycles when the 6809 is actually running
@ -239,10 +246,12 @@ begin
mem_gen : process(cpu_clk) mem_gen : process(cpu_clk)
begin begin
if rising_edge(cpu_clk) then if rising_edge(cpu_clk) then
if (cpu_clken = '1') then
memory_rd1 <= memory_rd; memory_rd1 <= memory_rd;
memory_wr1 <= memory_wr; memory_wr1 <= memory_wr;
memory_addr1 <= memory_addr; memory_addr1 <= memory_addr;
end if; end if;
end if;
end process; end process;
R_W_n <= '1' when memory_rd1 = '1' else '0' when memory_wr1 = '1' else R_W_n_int; R_W_n <= '1' when memory_rd1 = '1' else '0' when memory_wr1 = '1' else R_W_n_int;