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https://github.com/hoglet67/AtomBusMon.git
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Refactor: 2nd stage - bug fixes
Change-Id: Ic3bd520d0cc8b74f33068c53085229506d6968b2
This commit is contained in:
David Banks
parent
99c5f951d1
commit
6aeb0c7b8a
@ -10,7 +10,7 @@
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* VERSION and NAME are used in the start-up message
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********************************************************/
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#define VERSION "0.66"
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#define VERSION "0.70"
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#if (CPU == Z80)
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#define NAME "ICE-T80"
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@ -99,34 +99,40 @@ begin
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CLK2X_OUT => open
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);
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core : entity work.MOS6502CpuMonCore port map(
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => '1',
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cpu_clk => cpu_clk,
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cpu_clken => '1',
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IRQ_n => IRQ_n_sync,
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NMI_n => NMI_n_sync,
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Sync => Sync,
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Addr => Addr_int,
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R_W_n => R_W_n_int,
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Din => Din,
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Dout => Dout,
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SO_n => SO_n,
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Res_n => Res_n,
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core : entity work.MOS6502CpuMonCore
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => '1',
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cpu_clk => cpu_clk,
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cpu_clken => '1',
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IRQ_n => IRQ_n_sync,
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NMI_n => NMI_n_sync,
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Sync => Sync,
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Addr => Addr_int,
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R_W_n => R_W_n_int,
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Din => Din,
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Dout => Dout,
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SO_n => SO_n,
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Res_n_in => Res_n,
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Res_n_out => Res_n,
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Rdy => Rdy,
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trig => trig,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => sw1,
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nsw2 => nsw2,
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led3 => led3,
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led6 => led6,
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk
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);
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trig => trig,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => sw1,
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nsw2 => nsw2,
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led3 => led3,
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led6 => led6,
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk
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);
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sync_gen : process(cpu_clk)
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begin
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@ -21,11 +21,10 @@ use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity MOS6502CpuMonCore is
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false
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UseT65Core : boolean;
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UseAlanDCore : boolean
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);
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port (
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clock_avr : in std_logic;
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@ -44,7 +43,8 @@ entity MOS6502CpuMonCore is
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Din : in std_logic_vector(7 downto 0);
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Dout : out std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : inout std_logic;
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Res_n_in : in std_logic;
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Res_n_out : out std_logic;
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Rdy : in std_logic;
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-- External trigger inputs
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@ -72,6 +72,7 @@ end MOS6502CpuMonCore;
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architecture behavioral of MOS6502CpuMonCore is
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signal cpu_clken_ss : std_logic;
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signal Data : std_logic_vector(7 downto 0);
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signal Dout_int : std_logic_vector(7 downto 0);
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signal R_W_n_int : std_logic;
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@ -106,9 +107,9 @@ begin
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mon : entity work.BusMonCore port map (
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => '1',
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busmon_clken => busmon_clken,
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cpu_clk => cpu_clk,
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cpu_clken => '1',
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cpu_clken => cpu_clken,
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Addr => Addr_int,
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Data => Data,
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Rd_n => not R_W_n_int,
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@ -117,8 +118,8 @@ begin
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => open,
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nRSTin => Res_n,
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nRSTout => Res_n,
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nRSTin => Res_n_in,
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nRSTout => Res_n_out,
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CountCycle => CountCycle,
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trig => trig,
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lcd_rs => open,
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@ -164,8 +165,10 @@ begin
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last_pc_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (hold = '0') then
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last_PC <= Regs(63 downto 48);
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if (cpu_clken = '1') then
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if (hold = '0') then
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last_PC <= Regs(63 downto 48);
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end if;
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end if;
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end if;
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end process;
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@ -174,13 +177,15 @@ begin
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Regs1( 63 downto 48) <= last_PC;
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Regs1(255 downto 64) <= (others => '0');
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cpu_clken_ss <= (not hold) and cpu_clken;
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GenT65Core: if UseT65Core generate
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inst_t65: entity work.T65 port map (
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mode => "00",
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Abort_n => '1',
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SO_n => SO_n,
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Res_n => Res_n,
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Enable => not hold,
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Res_n => Res_n_in,
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Enable => cpu_clken_ss,
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Clk => cpu_clk,
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Rdy => '1',
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IRQ_n => IRQ_n,
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@ -197,9 +202,9 @@ begin
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GenAlanDCore: if UseAlanDCore generate
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inst_r65c02: entity work.r65c02 port map (
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reset => RES_n,
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reset => Res_n_in,
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clk => cpu_clk,
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enable => not hold,
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enable => cpu_clken_ss,
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nmi_n => NMI_n,
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irq_n => IRQ_n,
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di => unsigned(Din),
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@ -220,12 +225,14 @@ begin
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hold_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (Sync_int = '1') then
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-- stop after the opcode has been fetched
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hold <= SS_Single;
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elsif (SS_Step = '1') then
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-- start again when the single step command is issues
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hold <= '0';
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if (cpu_clken = '1') then
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if (Sync_int = '1') then
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-- stop after the opcode has been fetched
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hold <= SS_Single;
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elsif (SS_Step = '1') then
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-- start again when the single step command is issues
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hold <= '0';
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end if;
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end if;
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end if;
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end process;
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@ -239,9 +246,11 @@ begin
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mem_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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memory_rd1 <= memory_rd;
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memory_wr1 <= memory_wr;
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memory_addr1 <= memory_addr;
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if (cpu_clken = '1') then
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memory_rd1 <= memory_rd;
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memory_wr1 <= memory_wr;
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memory_addr1 <= memory_addr;
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end if;
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end if;
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end process;
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