mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2026-04-21 09:17:04 +00:00
Implemented IO watches/breakpoints; fixed a bug with stepping through CB/DD/ED/FD prefixed opcodes which have 2 M1 cycles; version not 0.47
Change-Id: Iad5cb406bd96a8020ccb65be5cd440bebec20481
This commit is contained in:
David Banks
+66
-81
@@ -25,18 +25,20 @@ use work.OhoPack.all ;
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entity BusMonCore is
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generic (
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num_comparators : integer := 8;
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reg_width : integer := 42;
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reg_width : integer := 46;
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fifo_width : integer := 72
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);
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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-- CPU Signals
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Addr : in std_logic_vector(15 downto 0);
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Data : in std_logic_vector(7 downto 0);
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Phi2 : in std_logic;
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Rd_n : in std_logic;
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Wr_n : in std_logic;
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RdIO_n : in std_logic;
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WrIO_n : in std_logic;
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Sync : in std_logic;
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Rdy : out std_logic;
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nRSTin : in std_logic;
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@@ -44,11 +46,11 @@ entity BusMonCore is
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CountCycle : in std_logic;
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-- 6502 Registers
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-- CPU Registers
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-- unused in pure bus monitor mode
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Regs : in std_logic_vector(255 downto 0);
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-- 6502 Memory Read/Write
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-- CPU Memory Read/Write
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-- unused in pure bus monitor mode
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RdMemOut : out std_logic;
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WrMemOut : out std_logic;
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@@ -296,52 +298,22 @@ begin
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Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
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-- Regs( 15 downto 8) when muxsel = 33 else
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-- Regs( 23 downto 16) when muxsel = 34 else
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-- Regs( 31 downto 24) when muxsel = 35 else
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-- Regs( 39 downto 32) when muxsel = 36 else
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-- Regs( 47 downto 40) when muxsel = 37 else
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-- Regs( 55 downto 48) when muxsel = 38 else
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-- Regs( 63 downto 56) when muxsel = 39 else
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-- Regs( 7 downto 64) when muxsel = 40 else
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-- Regs( 15 downto 72) when muxsel = 41 else
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-- Regs( 23 downto 80) when muxsel = 42 else
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-- Regs( 31 downto 88) when muxsel = 43 else
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-- Regs( 39 downto 96) when muxsel = 44 else
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-- Regs( 47 downto 104) when muxsel = 45 else
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-- Regs( 55 downto 112) when muxsel = 46 else
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-- Regs( 63 downto 120) when muxsel = 47 else
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-- Regs( 7 downto 128) when muxsel = 48 else
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-- Regs( 15 downto 136) when muxsel = 49 else
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-- Regs( 23 downto 144) when muxsel = 50 else
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-- Regs( 31 downto 24) when muxsel = 51 else
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-- Regs( 39 downto 32) when muxsel = 52 else
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-- Regs( 47 downto 40) when muxsel = 53 else
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-- Regs( 55 downto 48) when muxsel = 54 else
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-- Regs( 63 downto 56) when muxsel = 55 else
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-- Regs( 7 downto 0) when muxsel = 56 else
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-- Regs( 15 downto 8) when muxsel = 57 else
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-- Regs( 23 downto 16) when muxsel = 58 else
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-- Regs( 31 downto 24) when muxsel = 59 else
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-- Regs( 39 downto 32) when muxsel = 60 else
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-- Regs( 47 downto 40) when muxsel = 61 else
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-- Regs( 55 downto 48) when muxsel = 62 else
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-- Regs( 63 downto 56) when muxsel = 63 else
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--
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--
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-- "10101010";
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-- Combinatorial set of comparators to decode breakpoint/watch addresses
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brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync)
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brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n)
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variable i : integer;
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variable reg_addr : std_logic_vector(15 downto 0);
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variable reg_mask : std_logic_vector(15 downto 0);
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variable reg_mode_bi : std_logic;
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variable reg_mode_bar : std_logic;
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variable reg_mode_baw : std_logic;
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variable reg_mode_wi : std_logic;
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variable reg_mode_war : std_logic;
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variable reg_mode_waw : std_logic;
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variable reg_mode_bmr : std_logic;
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variable reg_mode_bmw : std_logic;
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variable reg_mode_bir : std_logic;
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variable reg_mode_biw : std_logic;
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variable reg_mode_bx : std_logic;
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variable reg_mode_wmr : std_logic;
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variable reg_mode_wmw : std_logic;
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variable reg_mode_wir : std_logic;
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variable reg_mode_wiw : std_logic;
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variable reg_mode_wx : std_logic;
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variable reg_mode_all : std_logic_vector(9 downto 0);
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variable bactive : std_logic;
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variable wactive : std_logic;
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variable status : std_logic_vector(3 downto 0);
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@@ -354,47 +326,60 @@ begin
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for i in 0 to num_comparators - 1 loop
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reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
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reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
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reg_mode_bi := brkpt_reg(i * reg_width + 32);
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reg_mode_bar := brkpt_reg(i * reg_width + 33);
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reg_mode_baw := brkpt_reg(i * reg_width + 34);
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reg_mode_wi := brkpt_reg(i * reg_width + 35);
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reg_mode_war := brkpt_reg(i * reg_width + 36);
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reg_mode_waw := brkpt_reg(i * reg_width + 37);
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trigval := brkpt_reg(i * reg_width + 38 + to_integer(unsigned(trig)));
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if (trigval = '1' and ((Addr and reg_mask) = reg_addr or
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(reg_mode_bi = '0' and reg_mode_bar = '0' and reg_mode_baw = '0' and
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(reg_mode_wi = '0' and reg_mode_war = '0' and reg_mode_waw = '0')))) then
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reg_mode_bmr := brkpt_reg(i * reg_width + 32);
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reg_mode_wmr := brkpt_reg(i * reg_width + 33);
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reg_mode_bmw := brkpt_reg(i * reg_width + 34);
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reg_mode_wmw := brkpt_reg(i * reg_width + 35);
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reg_mode_bir := brkpt_reg(i * reg_width + 36);
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reg_mode_wir := brkpt_reg(i * reg_width + 37);
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reg_mode_biw := brkpt_reg(i * reg_width + 38);
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reg_mode_wiw := brkpt_reg(i * reg_width + 39);
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reg_mode_bx := brkpt_reg(i * reg_width + 40);
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reg_mode_wx := brkpt_reg(i * reg_width + 41);
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reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
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trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
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if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
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if (Sync = '1') then
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if (reg_mode_bi = '1') then
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if (reg_mode_bx = '1') then
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bactive := '1';
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status := "0001";
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end if;
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if (reg_mode_wi = '1') then
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status := "1000";
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elsif (reg_mode_wx = '1') then
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wactive := '1';
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status := "1001";
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end if;
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else
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if (Rd_n = '0') then
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if (reg_mode_bar = '1') then
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bactive := '1';
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status := "0010";
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end if;
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if (reg_mode_war = '1') then
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wactive := '1';
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status := "1010";
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end if;
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elsif (Rd_n = '0') then
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if (reg_mode_bmr = '1') then
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bactive := '1';
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status := "0000";
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elsif (reg_mode_wmr = '1') then
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wactive := '1';
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status := "0001";
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end if;
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if (Wr_n = '0') then
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if (reg_mode_baw = '1') then
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bactive := '1';
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status := "0100";
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end if;
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if (reg_mode_waw = '1') then
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wactive := '1';
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status := "1100";
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end if;
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elsif (Wr_n = '0') then
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if (reg_mode_bmw = '1') then
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bactive := '1';
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status := "0010";
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elsif (reg_mode_wmw = '1') then
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wactive := '1';
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status := "0011";
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end if;
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end if;
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elsif (RdIO_n = '0') then
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if (reg_mode_bir = '1') then
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bactive := '1';
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status := "0100";
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elsif (reg_mode_wir = '1') then
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wactive := '1';
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status := "0101";
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end if;
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elsif (WrIO_n = '0') then
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if (reg_mode_biw = '1') then
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bactive := '1';
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status := "0110";
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elsif (reg_mode_wiw = '1') then
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wactive := '1';
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status := "0111";
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end if;
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end if;
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end if;
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end loop;
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end if;
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@@ -515,7 +500,7 @@ begin
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Rdy_int <= (not Sync);
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end if;
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-- 6502 Reset needs to be open collector
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-- CPU Reset needs to be open collector
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if (reset = '1') then
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nRSTout <= '0';
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else
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+39
-13
@@ -98,6 +98,7 @@ signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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signal SS_Step_held : std_logic;
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signal CountCycle : std_logic;
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signal skipNextOpcode : std_logic;
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signal Regs : std_logic_vector(255 downto 0);
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signal io_not_mem : std_logic;
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@@ -119,8 +120,14 @@ signal Read_n0 : std_logic;
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signal Read_n1 : std_logic;
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signal Write_n : std_logic;
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signal Write_n0 : std_logic;
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signal ReadIO_n : std_logic;
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signal ReadIO_n0 : std_logic;
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signal ReadIO_n1 : std_logic;
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signal WriteIO_n : std_logic;
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signal WriteIO_n0 : std_logic;
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signal Sync : std_logic;
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signal Sync0 : std_logic;
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signal Mem_IO_n : std_logic;
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signal nRST : std_logic;
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signal MemState : std_logic_vector(2 downto 0);
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@@ -145,6 +152,8 @@ begin
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Phi2 => busmon_clk,
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Rd_n => Read_n,
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Wr_n => Write_n,
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RdIO_n => ReadIO_n,
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WrIO_n => WriteIO_n,
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Sync => Sync,
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Rdy => Rdy,
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nRSTin => RESET_n_int,
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@@ -217,7 +226,7 @@ begin
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elsif rising_edge(CLK_n) then
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NMI_n_sync <= NMI_n;
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INT_n_sync <= INT_n;
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if (M1_n_int = '0' and TState = "001") then
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if (Sync0 = '1') then
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-- stop at the end of T1 instruction fetch
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SS_Step_held <= '0';
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elsif (SS_Step = '1') then
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@@ -227,19 +236,33 @@ begin
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end if;
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end process;
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-- Logic to ignore the second M1 in multi-byte opcodes
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skip_opcode_latch : process(CLK_n)
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begin
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if rising_edge(CLK_n) then
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if (M1_n_int = '0' and WAIT_n_int = '1' and TState = "010") then
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if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
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skipNextOpcode <= '1';
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else
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skipNextOpcode <= '0';
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end if;
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end if;
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end if;
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end process;
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-- For instruction breakpoints, we make the monitoring decision as early as possibe
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-- to allow time to stop the current instruction, which is possible because we don't
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-- really care about the data (it's re-read from memory by the disassembler).
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Sync0 <= not M1_n_int when TState = "001" else '0';
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Sync0 <= '1' when M1_n_int = '0' and TState = "001" and skipNextOpcode = '0' else '0';
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-- For reads/write breakpoints we make the monitoring decision in the middle of T2
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-- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
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-- but only if WAIT_n is '1' so we catch the right data.
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Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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Write_n0 <= not (WAIT_n_int and (not WR_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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-- These are useful for debugging IO Requests:
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-- Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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-- Write_n0 <= not ( ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
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ReadIO_n0 <= not (WAIT_n_int and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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WriteIO_n0 <= not ( ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
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-- Hold the monitoring decision so it is valid on the rising edge of the clock
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-- For instruction fetches and writes, the monitor sees these at the start of T3
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@@ -247,10 +270,13 @@ begin
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watch_gen : process(CLK_n)
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begin
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if falling_edge(CLK_n) then
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Sync <= Sync0;
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Read_n1 <= Read_n0;
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Read_n <= Read_n1;
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Write_n <= Write_n0;
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Sync <= Sync0;
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Read_n1 <= Read_n0;
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Read_n <= Read_n1;
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Write_n <= Write_n0;
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ReadIO_n1 <= ReadIO_n0;
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ReadIO_n <= ReadIO_n1;
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WriteIO_n <= WriteIO_n0;
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end if;
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end process;
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@@ -258,7 +284,7 @@ begin
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ex_data_latch : process(CLK_n)
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begin
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if rising_edge(CLK_n) then
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if (Sync = '1' or Write_n = '0') then
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if (Sync = '1' or Write_n = '0' or WriteIO_n = '0') then
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ex_data <= Data;
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end if;
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end if;
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@@ -268,7 +294,7 @@ begin
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rd_data_latch : process(CLK_n)
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begin
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if falling_edge(CLK_n) then
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if (Read_n1 = '0') then
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if (Read_n1 = '0' or ReadIO_n1 = '0') then
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rd_data <= Data;
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end if;
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memory_din <= Data;
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@@ -276,7 +302,7 @@ begin
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end process;
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-- Mux the data seen by the bus monitor appropriately
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mon_data <= rd_data when Read_n <= '0' else ex_data;
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mon_data <= rd_data when Read_n <= '0' or ReadIO_n = '0' else ex_data;
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-- Memory access
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Addr <= memory_addr when (state /= idle) else Addr_int;
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