Seperate ipcore directories for 250 and 500 parts
Change-Id: I726ff1bd3302a8918a71f069c0abf3251fe622aa
This commit is contained in:
David Banks
parent
cc0e8fb051
commit
74d3618b1a
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@ -21,18 +21,33 @@ build_500.log
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firmware/*.o
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firmware/*.bit
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firmware/avr_progmem.*
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ipcore_dir/WatchEvents.asy
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ipcore_dir/WatchEvents.gise
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ipcore_dir/WatchEvents.ncf
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ipcore_dir/WatchEvents.sym
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ipcore_dir/WatchEvents.vho
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ipcore_dir/WatchEvents/
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ipcore_dir/WatchEvents_flist.txt
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ipcore_dir/WatchEvents_xmdf.tcl
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ipcore_dir/gen_WatchEvents.tcl
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ipcore_dir/_xmsgs/
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ipcore_dir/coregen.cgp
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ipcore_dir/coregen.log
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ipcore_dir/create_WatchEvents.tcl
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ipcore_dir/edit_WatchEvents.tcl
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ipcore_dir/tmp/
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ipcore/250/WatchEvents.asy
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ipcore/250/WatchEvents.gise
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ipcore/250/WatchEvents.ncf
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ipcore/250/WatchEvents.sym
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ipcore/250/WatchEvents.vho
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ipcore/250/WatchEvents/
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ipcore/250/WatchEvents_flist.txt
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ipcore/250/WatchEvents_xmdf.tcl
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ipcore/250/gen_WatchEvents.tcl
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ipcore/250/_xmsgs/
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ipcore/250/coregen.cgp
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ipcore/250/coregen.log
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ipcore/250/create_WatchEvents.tcl
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ipcore/250/edit_WatchEvents.tcl
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ipcore/250/tmp/
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ipcore/500/WatchEvents.asy
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ipcore/500/WatchEvents.gise
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ipcore/500/WatchEvents.ncf
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ipcore/500/WatchEvents.sym
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ipcore/500/WatchEvents.vho
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ipcore/500/WatchEvents/
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ipcore/500/WatchEvents_flist.txt
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ipcore/500/WatchEvents_xmdf.tcl
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ipcore/500/gen_WatchEvents.tcl
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ipcore/500/_xmsgs/
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ipcore/500/coregen.cgp
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ipcore/500/coregen.log
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ipcore/500/create_WatchEvents.tcl
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ipcore/500/edit_WatchEvents.tcl
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ipcore/500/tmp/
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@ -221,7 +221,7 @@
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<file xil_pn:name="src/AtomBusMon.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore/250/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
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</file>
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@ -233,7 +233,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore/250/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -230,7 +230,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore/250/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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</file>
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@ -257,7 +257,7 @@
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<file xil_pn:name="src/250/AtomCpuMon.bmm" xil_pn:type="FILE_BMM">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore/250/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -230,7 +230,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore/250/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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</file>
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@ -261,7 +261,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore/250/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -34,7 +34,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore/250/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
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</file>
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@ -237,7 +237,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore/250/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -58,7 +58,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore/250/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
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</file>
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@ -257,7 +257,7 @@
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<file xil_pn:name="src/250/Z80CpuMon.bmm" xil_pn:type="FILE_BMM">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore/250/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -11,7 +11,7 @@ PROJECTS=`/bin/ls [A-Za-z0-9]*.xise`
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for i in $PROJECTS
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do
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cat $i | sed "s/xc3s250e/xc3s500e/" | sed "s#working/250#working/500#" | sed "s#src/250#src/500#" > `basename $i .xise`_500.xise
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cat $i | sed "s/xc3s250e/xc3s500e/" | sed "s#working/250#working/500#" | sed "s#src/250#src/500#" | sed "s#ipcore/250#ipcore/500#" > `basename $i .xise`_500.xise
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done
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# Reset the logfile
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File diff suppressed because one or more lines are too long
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@ -22,7 +22,7 @@
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2015 Xilinx, Inc. --
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-- (c) Copyright 1995-2016 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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@ -1,7 +1,7 @@
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##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Sat Oct 31 12:34:33 2015
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# Date: Mon Oct 24 15:28:50 2016
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#
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##############################################################
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#
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@ -52,8 +52,8 @@
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-10-31T12:36:59" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DA4EA14AB11DA8A53617EE9B6673579E" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-24T16:31:14" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A34A391A226EC90DB79C15E50562A6A1" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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File diff suppressed because one or more lines are too long
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@ -0,0 +1,280 @@
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--------------------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2016 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file WatchEvents.vhd when simulating
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-- the core, WatchEvents. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY WatchEvents IS
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END WatchEvents;
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ARCHITECTURE WatchEvents_a OF WatchEvents IS
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-- synthesis translate_off
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COMPONENT wrapped_WatchEvents
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END COMPONENT;
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-- Configuration specification
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FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
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GENERIC MAP (
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c_add_ngc_constraint => 0,
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c_application_type_axis => 0,
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c_application_type_rach => 0,
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c_application_type_rdch => 0,
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c_application_type_wach => 0,
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c_application_type_wdch => 0,
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c_application_type_wrch => 0,
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c_axi_addr_width => 32,
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c_axi_aruser_width => 1,
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c_axi_awuser_width => 1,
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c_axi_buser_width => 1,
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c_axi_data_width => 64,
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c_axi_id_width => 4,
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c_axi_ruser_width => 1,
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c_axi_type => 0,
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c_axi_wuser_width => 1,
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c_axis_tdata_width => 64,
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c_axis_tdest_width => 4,
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c_axis_tid_width => 8,
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c_axis_tkeep_width => 4,
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c_axis_tstrb_width => 4,
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c_axis_tuser_width => 4,
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c_axis_type => 0,
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c_common_clock => 1,
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c_count_type => 0,
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c_data_count_width => 10,
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c_default_value => "BlankString",
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c_din_width => 72,
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c_din_width_axis => 1,
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c_din_width_rach => 32,
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c_din_width_rdch => 64,
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c_din_width_wach => 32,
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c_din_width_wdch => 64,
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c_din_width_wrch => 2,
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c_dout_rst_val => "0",
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c_dout_width => 72,
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c_enable_rlocs => 0,
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c_enable_rst_sync => 1,
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c_error_injection_type => 0,
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c_error_injection_type_axis => 0,
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c_error_injection_type_rach => 0,
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c_error_injection_type_rdch => 0,
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c_error_injection_type_wach => 0,
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c_error_injection_type_wdch => 0,
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c_error_injection_type_wrch => 0,
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c_family => "spartan3",
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c_full_flags_rst_val => 0,
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c_has_almost_empty => 0,
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c_has_almost_full => 0,
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c_has_axi_aruser => 0,
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c_has_axi_awuser => 0,
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c_has_axi_buser => 0,
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c_has_axi_rd_channel => 0,
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c_has_axi_ruser => 0,
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c_has_axi_wr_channel => 0,
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c_has_axi_wuser => 0,
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c_has_axis_tdata => 0,
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c_has_axis_tdest => 0,
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c_has_axis_tid => 0,
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c_has_axis_tkeep => 0,
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c_has_axis_tlast => 0,
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c_has_axis_tready => 1,
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c_has_axis_tstrb => 0,
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c_has_axis_tuser => 0,
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c_has_backup => 0,
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c_has_data_count => 0,
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c_has_data_counts_axis => 0,
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c_has_data_counts_rach => 0,
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c_has_data_counts_rdch => 0,
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c_has_data_counts_wach => 0,
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c_has_data_counts_wdch => 0,
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c_has_data_counts_wrch => 0,
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c_has_int_clk => 0,
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c_has_master_ce => 0,
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c_has_meminit_file => 0,
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c_has_overflow => 0,
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c_has_prog_flags_axis => 0,
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c_has_prog_flags_rach => 0,
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c_has_prog_flags_rdch => 0,
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c_has_prog_flags_wach => 0,
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c_has_prog_flags_wdch => 0,
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c_has_prog_flags_wrch => 0,
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c_has_rd_data_count => 0,
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c_has_rd_rst => 0,
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c_has_rst => 0,
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c_has_slave_ce => 0,
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c_has_srst => 1,
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c_has_underflow => 0,
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c_has_valid => 0,
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c_has_wr_ack => 0,
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c_has_wr_data_count => 0,
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c_has_wr_rst => 0,
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c_implementation_type => 0,
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c_implementation_type_axis => 1,
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c_implementation_type_rach => 1,
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c_implementation_type_rdch => 1,
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c_implementation_type_wach => 1,
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c_implementation_type_wdch => 1,
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c_implementation_type_wrch => 1,
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c_init_wr_pntr_val => 0,
|
||||
c_interface_type => 0,
|
||||
c_memory_type => 1,
|
||||
c_mif_file_name => "BlankString",
|
||||
c_msgon_val => 1,
|
||||
c_optimization_mode => 0,
|
||||
c_overflow_low => 0,
|
||||
c_preload_latency => 0,
|
||||
c_preload_regs => 1,
|
||||
c_prim_fifo_type => "512x72",
|
||||
c_prog_empty_thresh_assert_val => 4,
|
||||
c_prog_empty_thresh_assert_val_axis => 1022,
|
||||
c_prog_empty_thresh_assert_val_rach => 1022,
|
||||
c_prog_empty_thresh_assert_val_rdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wach => 1022,
|
||||
c_prog_empty_thresh_assert_val_wdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wrch => 1022,
|
||||
c_prog_empty_thresh_negate_val => 5,
|
||||
c_prog_empty_type => 0,
|
||||
c_prog_empty_type_axis => 0,
|
||||
c_prog_empty_type_rach => 0,
|
||||
c_prog_empty_type_rdch => 0,
|
||||
c_prog_empty_type_wach => 0,
|
||||
c_prog_empty_type_wdch => 0,
|
||||
c_prog_empty_type_wrch => 0,
|
||||
c_prog_full_thresh_assert_val => 511,
|
||||
c_prog_full_thresh_assert_val_axis => 1023,
|
||||
c_prog_full_thresh_assert_val_rach => 1023,
|
||||
c_prog_full_thresh_assert_val_rdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wach => 1023,
|
||||
c_prog_full_thresh_assert_val_wdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wrch => 1023,
|
||||
c_prog_full_thresh_negate_val => 510,
|
||||
c_prog_full_type => 0,
|
||||
c_prog_full_type_axis => 0,
|
||||
c_prog_full_type_rach => 0,
|
||||
c_prog_full_type_rdch => 0,
|
||||
c_prog_full_type_wach => 0,
|
||||
c_prog_full_type_wdch => 0,
|
||||
c_prog_full_type_wrch => 0,
|
||||
c_rach_type => 0,
|
||||
c_rd_data_count_width => 10,
|
||||
c_rd_depth => 512,
|
||||
c_rd_freq => 1,
|
||||
c_rd_pntr_width => 9,
|
||||
c_rdch_type => 0,
|
||||
c_reg_slice_mode_axis => 0,
|
||||
c_reg_slice_mode_rach => 0,
|
||||
c_reg_slice_mode_rdch => 0,
|
||||
c_reg_slice_mode_wach => 0,
|
||||
c_reg_slice_mode_wdch => 0,
|
||||
c_reg_slice_mode_wrch => 0,
|
||||
c_synchronizer_stage => 2,
|
||||
c_underflow_low => 0,
|
||||
c_use_common_overflow => 0,
|
||||
c_use_common_underflow => 0,
|
||||
c_use_default_settings => 0,
|
||||
c_use_dout_rst => 1,
|
||||
c_use_ecc => 0,
|
||||
c_use_ecc_axis => 0,
|
||||
c_use_ecc_rach => 0,
|
||||
c_use_ecc_rdch => 0,
|
||||
c_use_ecc_wach => 0,
|
||||
c_use_ecc_wdch => 0,
|
||||
c_use_ecc_wrch => 0,
|
||||
c_use_embedded_reg => 0,
|
||||
c_use_fifo16_flags => 0,
|
||||
c_use_fwft_data_count => 1,
|
||||
c_valid_low => 0,
|
||||
c_wach_type => 0,
|
||||
c_wdch_type => 0,
|
||||
c_wr_ack_low => 0,
|
||||
c_wr_data_count_width => 10,
|
||||
c_wr_depth => 512,
|
||||
c_wr_depth_axis => 1024,
|
||||
c_wr_depth_rach => 16,
|
||||
c_wr_depth_rdch => 1024,
|
||||
c_wr_depth_wach => 16,
|
||||
c_wr_depth_wdch => 1024,
|
||||
c_wr_depth_wrch => 16,
|
||||
c_wr_freq => 1,
|
||||
c_wr_pntr_width => 9,
|
||||
c_wr_pntr_width_axis => 10,
|
||||
c_wr_pntr_width_rach => 4,
|
||||
c_wr_pntr_width_rdch => 10,
|
||||
c_wr_pntr_width_wach => 4,
|
||||
c_wr_pntr_width_wdch => 10,
|
||||
c_wr_pntr_width_wrch => 4,
|
||||
c_wr_response_latency => 1,
|
||||
c_wrch_type => 0
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_WatchEvents
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
srst => srst,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END WatchEvents_a;
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Mon Oct 24 16:22:59 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc3s500e
|
||||
SET devicefamily = spartan3e
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = vq100
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -4
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Common_Clock
|
||||
CSET component_name=WatchEvents
|
||||
CSET data_count=false
|
||||
CSET data_count_width=10
|
||||
CSET disable_timing_violations=false
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=4
|
||||
CSET empty_threshold_assert_value_axis=1022
|
||||
CSET empty_threshold_assert_value_rach=1022
|
||||
CSET empty_threshold_assert_value_rdch=1022
|
||||
CSET empty_threshold_assert_value_wach=1022
|
||||
CSET empty_threshold_assert_value_wdch=1022
|
||||
CSET empty_threshold_assert_value_wrch=1022
|
||||
CSET empty_threshold_negate_value=5
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=false
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=false
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=false
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=false
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_axis=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=0
|
||||
CSET full_threshold_assert_value=511
|
||||
CSET full_threshold_assert_value_axis=1023
|
||||
CSET full_threshold_assert_value_rach=1023
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=1023
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=1023
|
||||
CSET full_threshold_negate_value=510
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=72
|
||||
CSET input_depth=512
|
||||
CSET input_depth_axis=1024
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=Native
|
||||
CSET output_data_width=72
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=First_Word_Fall_Through
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=10
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Synchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=4
|
||||
CSET tstrb_width=4
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=true
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=10
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T12:39:56Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 61afebd2
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="WatchEvents.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="WatchEvents.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|WatchEvents|WatchEvents_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="WatchEvents.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/WatchEvents" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-24T17:25:23" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA470ACBBD8876116BA506A1F1C5A18A" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Loading…
Reference in New Issue