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LX9 support: in Z80CpuMon made the switch/led polarity configurable with generics

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Change-Id: I026bc8e56fe760b453edf970b33f6897a695d0d2
This commit is contained in:
David Banks
2017-07-25 19:18:59 +01:00
parent 17acd5afdd
commit 79d890bcb9
3 changed files with 25 additions and 9 deletions
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2
Z80CpuMonLX9Jason.xise
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@@ -365,7 +365,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

2
src/Z80CpuMon.ucf
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@@ -48,7 +48,7 @@ NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA) NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1) NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector # I/O's for test connector
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; #NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;

30
src/Z80CpuMon.vhd
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@@ -23,7 +23,10 @@ use work.OhoPack.all ;
entity Z80CpuMon is entity Z80CpuMon is
generic ( generic (
UseT80Core : boolean := true UseT80Core : boolean := true;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL
); );
port ( port (
clock49 : in std_logic; clock49 : in std_logic;
@@ -55,7 +58,7 @@ entity Z80CpuMon is
-- GODIL Switches -- GODIL Switches
sw1 : in std_logic; sw1 : in std_logic;
nsw2 : in std_logic; sw2 : in std_logic;
-- GODIL LEDs -- GODIL LEDs
led3 : out std_logic; led3 : out std_logic;
@@ -141,8 +144,21 @@ signal ex_data : std_logic_vector(7 downto 0);
signal rd_data : std_logic_vector(7 downto 0); signal rd_data : std_logic_vector(7 downto 0);
signal mon_data : std_logic_vector(7 downto 0); signal mon_data : std_logic_vector(7 downto 0);
signal led3_n : std_logic; -- led to indicate ext trig 0 is active
signal led6_n : std_logic; -- led to indicate ext trig 1 is active
signal led8_n : std_logic; -- led to indicate CPU has hit a breakpoint (and is stopped)
signal sw_interrupt_n : std_logic; -- switch to pause the CPU
signal sw_reset_n : std_logic; -- switch to reset the CPU
begin begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
sw_reset_n <= not sw1 when SW1ActiveHigh else sw1;
sw_interrupt_n <= not sw2 when SW2ActiveHigh else sw2;
led3 <= not led3_n when LEDsActiveHigh else led3_n;
led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map( inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49, CLKIN_IN => clock49,
CLKFX_OUT => clock_avr CLKFX_OUT => clock_avr
@@ -178,10 +194,10 @@ begin
avr_RxD => avr_RxD, avr_RxD => avr_RxD,
avr_TxD => avr_TxD, avr_TxD => avr_TxD,
sw1 => '0', sw1 => '0',
nsw2 => nsw2, nsw2 => sw_interrupt_n,
led3 => led3, led3 => led3_n,
led6 => led6, led6 => led6_n,
led8 => led8, led8 => led8_n,
tmosi => tmosi, tmosi => tmosi,
tdin => tdin, tdin => tdin,
tcclk => tcclk, tcclk => tcclk,
@@ -384,7 +400,7 @@ begin
end if; end if;
end process; end process;
RESET_n_int <= RESET_n and (not sw1) and nRST; RESET_n_int <= RESET_n and sw_reset_n and nRST;
test1 <= TState(0); test1 <= TState(0);
test2 <= TState(1); test2 <= TState(1);