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R65C02: Whitespace only

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Change-Id: I19aa6962d48206dc0eb75cabfa9f230e8872822d
This commit is contained in:
David Banks 2021-03-13 11:12:37 +00:00
parent 709c73999b
commit 839d510af9
1 changed files with 1399 additions and 1333 deletions
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272
src/AlanD/R65Cx2.vhd
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@ -48,9 +48,6 @@ end R65C02;
architecture Behavioral of R65C02 is architecture Behavioral of R65C02 is
-- signal counter : unsigned(27 downto 0);
-- signal mask_irq : std_logic;
-- signal mask_enable : std_logic;
-- Statemachine -- Statemachine
type cpuCycles is ( type cpuCycles is (
@ -74,6 +71,7 @@ architecture Behavioral of R65C02 is
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd cycleEnd
); );
signal theCpuCycle : cpuCycles; signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles; signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean; signal updateRegisters : boolean;
@ -84,6 +82,7 @@ architecture Behavioral of R65C02 is
signal soReg : std_logic; -- SO pin edge detection signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding -- Opcode decoding
constant opcUpdateA : integer := 0; constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1; constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2; constant opcUpdateY : integer := 2;
@ -112,7 +111,6 @@ architecture Behavioral of R65C02 is
constant opcRti : integer := 24; constant opcRti : integer := 24;
constant opcIRQ : integer := 25; constant opcIRQ : integer := 25;
constant opcInA : integer := 26; constant opcInA : integer := 26;
constant opcInBrk : integer := 27; constant opcInBrk : integer := 27;
constant opcInX : integer := 28; constant opcInX : integer := 28;
@ -129,7 +127,7 @@ architecture Behavioral of R65C02 is
constant aluMode2From : integer := 38; constant aluMode2From : integer := 38;
-- --
constant aluMode2To : integer := 40; constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41; constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42; constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43; constant opcInCpy : integer := 43;
@ -200,8 +198,6 @@ architecture Behavioral of R65C02 is
constant rts : addrDef := "0000101000100100"; constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010"; constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001"; constant brk : addrDef := "1000111000000001";
-- constant irq : addrDef := "0000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00"; constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu -- A = accu
@ -259,9 +255,7 @@ architecture Behavioral of R65C02 is
constant aluModeOra : aluMode2 := "101"; constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110"; constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111"; constant aluModeNoF : aluMode2 := "111";
--aluModeBRK
--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
constant aluInp : aluMode := aluModeInp & aluModePss & "---"; constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---"; constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---"; constant aluInc : aluMode := aluModeInc & aluModePss & "---";
@ -285,14 +279,15 @@ architecture Behavioral of R65C02 is
constant aluXXX : aluMode := (others => '-'); constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None -- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0"; constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1"; constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-"; constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43); subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := ( constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A -- +------- Update register A
-- |+------ Update register X -- |+------ Update register X
@ -595,6 +590,7 @@ architecture Behavioral of R65C02 is
nextAddrStack, nextAddrStack,
nextAddrRelative nextAddrRelative
); );
signal nextAddr : nextAddrDef; signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0); signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0); signal myAddrIncr : unsigned(15 downto 0);
@ -632,11 +628,12 @@ architecture Behavioral of R65C02 is
signal aluZ : std_logic; signal aluZ : std_logic;
signal aluV : std_logic; signal aluV : std_logic;
signal aluN : std_logic; signal aluN : std_logic;
-- Indexing -- Indexing
signal indexOut : unsigned(8 downto 0); signal indexOut : unsigned(8 downto 0);
signal realbrk : std_logic;
begin begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S) processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0); variable temp : unsigned(7 downto 0);
begin begin
@ -721,7 +718,6 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
tsxBits := (others => '-'); tsxBits := (others => '-');
R <= '1'; R <= '1';
-- Shift unit -- Shift unit
case opcInfo(aluMode1From to aluMode1To) is case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput; when aluModeInp => rmwBits := C & aluInput;
@ -754,10 +750,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
when others => ninebits := rmwBits; when others => ninebits := rmwBits;
end case; end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1); varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
@ -786,7 +780,6 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
-- v Set if signed overflow; cleared if valid signed result. -- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared. -- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result -- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc => when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag. -- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then if D = '1' then
@ -797,7 +790,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
end if; end if;
end if; end if;
end if; end if;
when others => null; when others =>
null;
end case; end case;
case opcInfo(aluMode2From to aluMode2To) is case opcInfo(aluMode2From to aluMode2To) is
@ -823,7 +817,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
ninebits(8 downto 4) := ninebits(8 downto 4) - 6; ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if; end if;
end if; end if;
when others => null; when others =>
null;
end case; end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode -- fix n and z flag for 65c02 adc sbc instructions in decimal mode
@ -846,7 +841,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
end if; end if;
varN := ninebits(7); varN := ninebits(7);
end if; end if;
when others => null; when others =>
null;
end case; end case;
-- DMB Remove Pipelining -- DMB Remove Pipelining
@ -984,13 +980,16 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
nextCpuCycle <= opcodeFetch; nextCpuCycle <= opcodeFetch;
case theCpuCycle is case theCpuCycle is
when opcodeFetch => when opcodeFetch =>
if nextOpcode(1 downto 0) = "11" then if nextOpcode(1 downto 0) = "11" then
nextCpuCycle <= opcodeFetch; nextCpuCycle <= opcodeFetch;
else else
nextCpuCycle <= cycle2; nextCpuCycle <= cycle2;
end if; end if;
when cycle2 => if opcInfo(opcBranch) = '1' then
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
@ -1031,7 +1030,9 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
elsif opcInfo(opcJump) = '1' then elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump; nextCpuCycle <= cycleJump;
end if; end if;
when cycle3 => nextCpuCycle <= cycleRead;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite; nextCpuCycle <= cyclePreWrite;
@ -1046,14 +1047,21 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
nextCpuCycle <= cycleRead2; nextCpuCycle <= cycleRead2;
end if; end if;
end if; end if;
when cyclePreIndirect => nextCpuCycle <= cycleIndirect; when cyclePreIndirect =>
when cycleIndirect => nextCpuCycle <= cycle3; nextCpuCycle <= cycleIndirect;
when cycleBranchTaken => if indexOut(8) /= T(7) then
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage; nextCpuCycle <= cycleBranchPage;
end if; end if;
when cyclePreRead => if opcInfo(opcZeroPage) = '1' then when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2; nextCpuCycle <= cycleRead2;
end if; end if;
when cycleRead => when cycleRead =>
if opcInfo(opcJump) = '1' then if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump; nextCpuCycle <= cycleJump;
@ -1065,33 +1073,51 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
nextCpuCycle <= cycleRead2; nextCpuCycle <= cycleRead2;
end if; end if;
end if; end if;
when cycleRead2 => if opcInfo(opcRmw) = '1' then
when cycleRead2 =>
if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw; nextCpuCycle <= cycleRmw;
end if; end if;
when cycleRmw => nextCpuCycle <= cycleWrite;
when cyclePreWrite => nextCpuCycle <= cycleWrite; when cycleRmw =>
when cycleStack1 => nextCpuCycle <= cycleRead; nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2; nextCpuCycle <= cycleStack2;
end if; end if;
when cycleStack2 => nextCpuCycle <= cycleStack3;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead; nextCpuCycle <= cycleRead;
end if; end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump; nextCpuCycle <= cycleJump;
end if; end if;
when cycleStack3 => nextCpuCycle <= cycleRead;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump; nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4; nextCpuCycle <= cycleStack4;
end if; end if;
when cycleStack4 => nextCpuCycle <= cycleRead;
when cycleJump => if opcInfo(opcIncrAfter) = '1' then when cycleStack4 =>
nextCpuCycle <= cycleRead;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd; nextCpuCycle <= cycleEnd;
end if; end if;
when others => null;
when others =>
null;
end case; end case;
end process; end process;
@ -1103,7 +1129,8 @@ calcT: process(clk)
if rising_edge(clk) then if rising_edge(clk) then
if enable = '1' then if enable = '1' then
case theCpuCycle is case theCpuCycle is
when cycle2 => T <= di; when cycle2 =>
T <= di;
when cycleStack1 | cycleStack2 => when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
@ -1112,8 +1139,10 @@ calcT: process(clk)
T <= di; T <= di;
end if; end if;
end if; end if;
when cycleIndirect | cycleRead | cycleRead2 => T <= di; when cycleIndirect | cycleRead | cycleRead2 =>
when others => null; T <= di;
when others =>
null;
end case; end case;
end if; end if;
end if; end if;
@ -1204,6 +1233,7 @@ calcT: process(clk)
end if; end if;
end if; end if;
end process; end process;
-- ----------------------------------------------------------------------- -- -----------------------------------------------------------------------
-- D flag -- D flag
-- ----------------------------------------------------------------------- -- -----------------------------------------------------------------------
@ -1271,16 +1301,22 @@ calcT: process(clk)
updateFlag := true; updateFlag := true;
end if; end if;
when cycleStack2 => updateFlag := true; when cycleStack2 =>
when cycleStack3 => updateFlag := true; updateFlag := true;
when cycleStack4 => updateFlag := true; when cycleStack3 =>
when cycleRead => if opcInfo(opcRti) = '1' then updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true; updateFlag := true;
end if; end if;
when cycleWrite => if opcInfo(opcStackData) = '1' then when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true; updateFlag := true;
end if; end if;
when others => null; when others =>
null;
end case; end case;
if updateFlag then if updateFlag then
@ -1307,22 +1343,25 @@ calcDo: process(clk)
if enable = '1' then if enable = '1' then
doReg <= aluRmwOut; doReg <= aluRmwOut;
case nextCpuCycle is case nextCpuCycle is
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then when cycleStack2 =>
if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8); doReg <= myAddrIncr(15 downto 8);
else else
doReg <= PC(15 downto 8); doReg <= PC(15 downto 8);
end if; end if;
when cycleStack3 => doReg <= PC(7 downto 0); when cycleStack3 =>
when cycleRmw => doReg <= di; -- Read-modify-write write old value first. doReg <= PC(7 downto 0);
when others => null; when cycleRmw =>
doReg <= di; -- Read-modify-write write old value first.
when others =>
null;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
do <= doReg; do <= doReg;
-- ----------------------------------------------------------------------- -- -----------------------------------------------------------------------
-- Write enable -- Write enable
-- ----------------------------------------------------------------------- -- -----------------------------------------------------------------------
@ -1340,9 +1379,12 @@ calcWe: process(clk)
if opcInfo(opcStackUp) = '0' then if opcInfo(opcStackUp) = '0' then
theWe <= '0'; theWe <= '0';
end if; end if;
when cycleRmw => theWe <= '0'; when cycleRmw =>
when cycleWrite => theWe <= '0'; theWe <= '0';
when others => null; when cycleWrite =>
theWe <= '0';
when others =>
null;
end case; end case;
end if; end if;
end if; end if;
@ -1358,18 +1400,22 @@ calcPC: process(clk)
if rising_edge(clk) then if rising_edge(clk) then
if enable = '1' then if enable = '1' then
case theCpuCycle is case theCpuCycle is
when opcodeFetch => PC <= myAddr; when opcodeFetch =>
when cycle2 => if irqActive = '0' then PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr; PC <= myAddrIncr;
else else
PC <= myAddr; PC <= myAddr;
end if; end if;
end if; end if;
when cycle3 => if opcInfo(opcAbsolute) = '1' then when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr; PC <= myAddrIncr;
end if; end if;
when others => null; when others =>
null;
end case; end case;
end if; end if;
end if; end if;
@ -1383,7 +1429,8 @@ calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin begin
nextAddr <= nextAddrIncr; nextAddr <= nextAddrIncr;
case theCpuCycle is case theCpuCycle is
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then when cycle2 =>
if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack; nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr; nextAddr <= nextAddrIncr;
@ -1396,67 +1443,72 @@ calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
else else
nextAddr <= nextAddrHold; nextAddr <= nextAddrHold;
end if; end if;
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then when cycle3 =>
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs; nextAddr <= nextAddrAbs;
else else
nextAddr <= nextAddrAbsIndexed; nextAddr <= nextAddrAbsIndexed;
end if; end if;
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed; when cyclePreIndirect =>
when cycleIndirect => nextAddr <= nextAddrIncrL; nextAddr <= nextAddrZPIndexed;
when cycleBranchTaken => nextAddr <= nextAddrRelative; when cycleIndirect =>
when cycleBranchPage => if T(7) = '0' then nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH; nextAddr <= nextAddrIncrH;
else else
nextAddr <= nextAddrDecrH; nextAddr <= nextAddrDecrH;
end if; end if;
when cyclePreRead => nextAddr <= nextAddrZPIndexed; when cyclePreRead =>
when cycleRead => nextAddr <= nextAddrPc; nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncr; nextAddr <= nextAddrIncr;
--nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH; nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold; nextAddr <= nextAddrHold;
end if; end if;
when cycleRead2 => nextAddr <= nextAddrPc; when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold; nextAddr <= nextAddrHold;
end if; end if;
when cycleRmw => nextAddr <= nextAddrHold; when cycleRmw =>
when cyclePreWrite => nextAddr <= nextAddrHold; nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed; nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH; nextAddr <= nextAddrIncrH;
end if; end if;
when cycleWrite => nextAddr <= nextAddrPc; when cycleWrite =>
when cycleStack1 => nextAddr <= nextAddrStack; nextAddr <= nextAddrPc;
when cycleStack2 => nextAddr <= nextAddrStack; when cycleStack1 =>
when cycleStack3 => nextAddr <= nextAddrStack; nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc; nextAddr <= nextAddrPc;
end if; end if;
when cycleStack4 => nextAddr <= nextAddrIrq; when cycleStack4 =>
when cycleJump => nextAddr <= nextAddrAbs; nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others => null; when others =>
null;
end case; end case;
if reset = '0' then if reset = '0' then
nextAddr <= nextAddrReset; nextAddr <= nextAddrReset;
end if; end if;
end process; end process;
indexAlu: process(opcInfo, myAddr, T, X, Y) indexAlu: process(opcInfo, myAddr, T, X, Y)
begin begin
if opcInfo(indexX) = '1' then if opcInfo(indexX) = '1' then
@ -1475,28 +1527,41 @@ calcAddr: process(clk)
if rising_edge(clk) then if rising_edge(clk) then
if enable = '1' then if enable = '1' then
case nextAddr is case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr; when nextAddrIncr =>
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); myAddr <= myAddrIncr;
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; when nextAddrIncrL =>
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrPc => myAddr <= PC; when nextAddrIncrH =>
when nextAddrIrq =>myAddr <= X"FFFE"; myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH =>
myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc =>
myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then if nmiReg = '0' then
myAddr <= X"FFFA"; myAddr <= X"FFFA";
end if; end if;
when nextAddrReset => myAddr <= X"FFFC"; when nextAddrReset =>
when nextAddrAbs => myAddr <= di & T; myAddr <= X"FFFC";
when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0); when nextAddrAbs =>
myAddr <= di & T;
when nextAddrAbsIndexed =>
if theOpcode = x"7C" then if theOpcode = x"7C" then
myAddr <= (di & T) + (x"00"& X); myAddr <= (di & T) + (x"00"& X);
else else
myAddr <= di & indexOut(7 downto 0); myAddr <= di & indexOut(7 downto 0);
end if; end if;
when nextAddrZeroPage => myAddr <= "00000000" & di; when nextAddrZeroPage =>
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); myAddr <= "00000000" & di;
when nextAddrStack => myAddr <= "00000001" & S; when nextAddrZPIndexed =>
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); myAddr <= "00000000" & indexOut(7 downto 0);
when others => null; when nextAddrStack =>
myAddr <= "00000001" & S;
when nextAddrRelative =>
myAddr(7 downto 0) <= indexOut(7 downto 0);
when others =>
null;
end case; end case;
end if; end if;
end if; end if;
@ -1511,11 +1576,12 @@ calcAddr: process(clk)
-- --
-- calcsync: process(clk) -- calcsync: process(clk)
-- begin -- begin
--
-- if enable = '1' then -- if enable = '1' then
-- case theCpuCycle is -- case theCpuCycle is
-- when opcodeFetch => sync <= '1'; -- when opcodeFetch =>
-- when others => sync <= '0'; -- sync <= '1';
-- when others =>
-- sync <= '0';
-- end case; -- end case;
-- end if; -- end if;
-- end process; -- end process;