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R65C02: Whitespace only
Change-Id: I19aa6962d48206dc0eb75cabfa9f230e8872822d
This commit is contained in:
David Banks
parent
709c73999b
commit
839d510af9
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@ -48,9 +48,6 @@ end R65C02;
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architecture Behavioral of R65C02 is
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-- signal counter : unsigned(27 downto 0);
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-- signal mask_irq : std_logic;
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-- signal mask_enable : std_logic;
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-- Statemachine
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type cpuCycles is (
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@ -74,16 +71,18 @@ architecture Behavioral of R65C02 is
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cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
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cycleEnd
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);
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signal theCpuCycle : cpuCycles;
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signal nextCpuCycle : cpuCycles;
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signal updateRegisters : boolean;
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signal processIrq : std_logic;
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signal nmiReg: std_logic;
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signal nmiEdge: std_logic;
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signal nmiReg : std_logic;
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signal nmiEdge : std_logic;
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signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
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signal soReg : std_logic; -- SO pin edge detection
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-- Opcode decoding
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constant opcUpdateA : integer := 0;
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constant opcUpdateX : integer := 1;
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constant opcUpdateY : integer := 2;
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@ -112,7 +111,6 @@ architecture Behavioral of R65C02 is
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constant opcRti : integer := 24;
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constant opcIRQ : integer := 25;
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constant opcInA : integer := 26;
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constant opcInBrk : integer := 27;
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constant opcInX : integer := 28;
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@ -129,7 +127,7 @@ architecture Behavioral of R65C02 is
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constant aluMode2From : integer := 38;
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--
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constant aluMode2To : integer := 40;
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--
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constant opcInCmp : integer := 41;
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constant opcInCpx : integer := 42;
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constant opcInCpy : integer := 43;
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@ -200,8 +198,6 @@ architecture Behavioral of R65C02 is
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constant rts : addrDef := "0000101000100100";
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constant rti : addrDef := "0000111000100010";
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constant brk : addrDef := "1000111000000001";
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-- constant irq : addrDef := "0000111000000001";
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-- constant : unsigned(0 to 0) := "0";
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constant xxxxxxxx : addrDef := "----------0---00";
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-- A = accu
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@ -259,9 +255,7 @@ architecture Behavioral of R65C02 is
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constant aluModeOra : aluMode2 := "101";
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constant aluModeEor : aluMode2 := "110";
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constant aluModeNoF : aluMode2 := "111";
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--aluModeBRK
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--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
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--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
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constant aluInp : aluMode := aluModeInp & aluModePss & "---";
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constant aluP : aluMode := aluModeP & aluModePss & "---";
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constant aluInc : aluMode := aluModeInc & aluModePss & "---";
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@ -285,14 +279,15 @@ architecture Behavioral of R65C02 is
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constant aluXXX : aluMode := (others => '-');
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-- Stack operations. Push/Pop/None
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constant stackInc : unsigned(0 to 0) := "0";
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constant stackDec : unsigned(0 to 0) := "1";
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constant stackXXX : unsigned(0 to 0) := "-";
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subtype decodedBitsDef is unsigned(0 to 43);
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type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
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constant opcodeInfoTable : opcodeInfoTableDef := (
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-- +------- Update register A
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-- |+------ Update register X
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@ -595,6 +590,7 @@ architecture Behavioral of R65C02 is
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nextAddrStack,
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nextAddrRelative
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);
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signal nextAddr : nextAddrDef;
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signal myAddr : unsigned(15 downto 0);
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signal myAddrIncr : unsigned(15 downto 0);
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@ -607,19 +603,19 @@ architecture Behavioral of R65C02 is
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-- Buffer register
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signal T : unsigned(7 downto 0);
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-- General registers
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signal A: unsigned(7 downto 0); -- Accumulator
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signal X: unsigned(7 downto 0); -- Index X
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signal Y: unsigned(7 downto 0); -- Index Y
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signal S: unsigned(7 downto 0); -- stack pointer
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signal A : unsigned(7 downto 0); -- Accumulator
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signal X : unsigned(7 downto 0); -- Index X
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signal Y : unsigned(7 downto 0); -- Index Y
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signal S : unsigned(7 downto 0); -- stack pointer
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-- Status register
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signal C: std_logic; -- Carry
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signal Z: std_logic; -- Zero flag
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signal I: std_logic; -- Interrupt flag
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signal D: std_logic; -- Decimal mode
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signal B: std_logic; -- Break software interrupt
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signal R: std_logic; -- always 1
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signal V: std_logic; -- Overflow
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signal N: std_logic; -- Negative
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signal C : std_logic; -- Carry
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signal Z : std_logic; -- Zero flag
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signal I : std_logic; -- Interrupt flag
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signal D : std_logic; -- Decimal mode
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signal B : std_logic; -- Break software interrupt
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signal R : std_logic; -- always 1
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signal V : std_logic; -- Overflow
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signal N : std_logic; -- Negative
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-- ALU
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-- ALU input
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@ -632,12 +628,13 @@ architecture Behavioral of R65C02 is
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signal aluZ : std_logic;
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signal aluV : std_logic;
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signal aluN : std_logic;
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-- Indexing
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signal indexOut : unsigned(8 downto 0);
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signal realbrk : std_logic;
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begin
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processAluInput: process(clk, opcInfo, A, X, Y, T, S)
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processAluInput: process(clk, opcInfo, A, X, Y, T, S)
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variable temp : unsigned(7 downto 0);
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begin
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temp := (others => '1');
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@ -668,7 +665,7 @@ processAluInput: process(clk, opcInfo, A, X, Y, T, S)
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end process;
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processCmpInput: process(clk, opcInfo, A, X, Y)
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processCmpInput: process(clk, opcInfo, A, X, Y)
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variable temp : unsigned(7 downto 0);
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begin
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temp := (others => '1');
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@ -704,11 +701,11 @@ processCmpInput: process(clk, opcInfo, A, X, Y)
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--hardware interrupts IRQ & NMI will push the B flag as being 0.
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processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
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variable lowBits: unsigned(5 downto 0);
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variable nineBits: unsigned(8 downto 0);
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variable rmwBits: unsigned(8 downto 0);
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variable tsxBits: unsigned(8 downto 0);
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processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
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variable lowBits : unsigned(5 downto 0);
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variable nineBits : unsigned(8 downto 0);
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variable rmwBits : unsigned(8 downto 0);
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variable tsxBits : unsigned(8 downto 0);
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variable varC : std_logic;
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variable varZ : std_logic;
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@ -721,7 +718,6 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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tsxBits := (others => '-');
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R <= '1';
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-- Shift unit
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case opcInfo(aluMode1From to aluMode1To) is
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when aluModeInp => rmwBits := C & aluInput;
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@ -754,10 +750,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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when others => ninebits := rmwBits;
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end case;
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varV := aluInput(6); -- Default for BIT / PLP / RTI
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if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
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varZ := rmwBits(1);
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elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
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@ -786,7 +780,6 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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-- v Set if signed overflow; cleared if valid signed result.
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-- z Set if result is zero; else cleared.
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-- c Set if unsigned overflow; cleared if valid unsigned result
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when aluModeAdc =>
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-- decimal mode low bits correction, is done after setting Z flag.
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if D = '1' then
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@ -797,7 +790,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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end if;
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end if;
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end if;
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when others => null;
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when others =>
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null;
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end case;
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case opcInfo(aluMode2From to aluMode2To) is
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@ -823,7 +817,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
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end if;
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end if;
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when others => null;
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when others =>
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null;
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end case;
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-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
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@ -846,7 +841,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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end if;
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varN := ninebits(7);
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end if;
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when others => null;
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when others =>
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null;
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end case;
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-- DMB Remove Pipelining
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@ -861,7 +857,7 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
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end process;
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calcInterrupt: process(clk)
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calcInterrupt: process(clk)
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begin
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if rising_edge(clk) then
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if enable = '1' then
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@ -895,7 +891,7 @@ calcInterrupt: process(clk)
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-- end if;
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-- end process;
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calcNextOpcode: process(clk, di, reset, processIrq)
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calcNextOpcode: process(clk, di, reset, processIrq)
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variable myNextOpcode : unsigned(7 downto 0);
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begin
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-- Next opcode is read from input unless a reset or IRQ is pending.
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@ -921,7 +917,7 @@ calcNextOpcode: process(clk, di, reset, processIrq)
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-- Read bits and flags from opcodeInfoTable and store in opcInfo.
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-- This info is used to control the execution of the opcode.
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calcOpcInfo: process(clk)
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calcOpcInfo: process(clk)
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begin
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if rising_edge(clk) then
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if enable = '1' then
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@ -932,7 +928,7 @@ calcOpcInfo: process(clk)
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end if;
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end process;
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calcTheOpcode: process(clk)
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calcTheOpcode: process(clk)
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begin
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if rising_edge(clk) then
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if enable = '1' then
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@ -979,18 +975,21 @@ calcTheOpcode: process(clk)
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-- Determine the next cpu cycle. After the last cycle we always
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-- go to opcodeFetch to get the next opcode.
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calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut, T, N, V, C, Z)
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calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut, T, N, V, C, Z)
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begin
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nextCpuCycle <= opcodeFetch;
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case theCpuCycle is
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when opcodeFetch =>
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if nextOpcode(1 downto 0) = "11" then
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nextCpuCycle <= opcodeFetch;
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else
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nextCpuCycle <= cycle2;
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end if;
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when cycle2 => if opcInfo(opcBranch) = '1' then
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when cycle2 =>
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if opcInfo(opcBranch) = '1' then
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if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
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or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
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or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
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@ -1031,7 +1030,9 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
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elsif opcInfo(opcJump) = '1' then
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nextCpuCycle <= cycleJump;
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end if;
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when cycle3 => nextCpuCycle <= cycleRead;
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when cycle3 =>
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nextCpuCycle <= cycleRead;
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if opcInfo(opcWrite) = '1' then
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if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
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nextCpuCycle <= cyclePreWrite;
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@ -1046,14 +1047,21 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
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nextCpuCycle <= cycleRead2;
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end if;
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end if;
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when cyclePreIndirect => nextCpuCycle <= cycleIndirect;
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when cycleIndirect => nextCpuCycle <= cycle3;
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when cycleBranchTaken => if indexOut(8) /= T(7) then
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when cyclePreIndirect =>
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nextCpuCycle <= cycleIndirect;
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when cycleIndirect =>
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nextCpuCycle <= cycle3;
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when cycleBranchTaken =>
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if indexOut(8) /= T(7) then
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nextCpuCycle <= cycleBranchPage;
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end if;
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when cyclePreRead => if opcInfo(opcZeroPage) = '1' then
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when cyclePreRead =>
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if opcInfo(opcZeroPage) = '1' then
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nextCpuCycle <= cycleRead2;
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end if;
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when cycleRead =>
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if opcInfo(opcJump) = '1' then
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nextCpuCycle <= cycleJump;
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@ -1065,45 +1073,64 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut,
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nextCpuCycle <= cycleRead2;
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end if;
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end if;
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when cycleRead2 => if opcInfo(opcRmw) = '1' then
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when cycleRead2 =>
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if opcInfo(opcRmw) = '1' then
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nextCpuCycle <= cycleRmw;
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end if;
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when cycleRmw => nextCpuCycle <= cycleWrite;
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when cyclePreWrite => nextCpuCycle <= cycleWrite;
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when cycleStack1 => nextCpuCycle <= cycleRead;
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when cycleRmw =>
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nextCpuCycle <= cycleWrite;
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when cyclePreWrite =>
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nextCpuCycle <= cycleWrite;
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when cycleStack1 =>
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nextCpuCycle <= cycleRead;
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if opcInfo(opcStackAddr) = '1' then
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nextCpuCycle <= cycleStack2;
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end if;
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when cycleStack2 => nextCpuCycle <= cycleStack3;
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when cycleStack2 =>
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nextCpuCycle <= cycleStack3;
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if opcInfo(opcRti) = '1' then
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nextCpuCycle <= cycleRead;
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end if;
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if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
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nextCpuCycle <= cycleJump;
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end if;
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when cycleStack3 => nextCpuCycle <= cycleRead;
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when cycleStack3 =>
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nextCpuCycle <= cycleRead;
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if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
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nextCpuCycle <= cycleJump;
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elsif opcInfo(opcStackAddr) = '1' then
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nextCpuCycle <= cycleStack4;
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end if;
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when cycleStack4 => nextCpuCycle <= cycleRead;
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when cycleJump => if opcInfo(opcIncrAfter) = '1' then
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when cycleStack4 =>
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nextCpuCycle <= cycleRead;
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when cycleJump =>
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if opcInfo(opcIncrAfter) = '1' then
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nextCpuCycle <= cycleEnd;
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end if;
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when others => null;
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when others =>
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null;
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end case;
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end process;
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-- -----------------------------------------------------------------------
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-- T register
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-- -----------------------------------------------------------------------
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calcT: process(clk)
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calcT: process(clk)
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begin
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if rising_edge(clk) then
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if enable = '1' then
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case theCpuCycle is
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when cycle2 => T <= di;
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when cycle2 =>
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T <= di;
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when cycleStack1 | cycleStack2 =>
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if opcInfo(opcStackUp) = '1' then
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if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
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@ -1112,8 +1139,10 @@ calcT: process(clk)
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T <= di;
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end if;
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end if;
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when cycleIndirect | cycleRead | cycleRead2 => T <= di;
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when others => null;
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when cycleIndirect | cycleRead | cycleRead2 =>
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T <= di;
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when others =>
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null;
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end case;
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end if;
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end if;
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@ -1204,6 +1233,7 @@ calcT: process(clk)
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end if;
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end if;
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end process;
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-- -----------------------------------------------------------------------
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-- D flag
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-- -----------------------------------------------------------------------
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@ -1271,16 +1301,22 @@ calcT: process(clk)
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updateFlag := true;
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end if;
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when cycleStack2 => updateFlag := true;
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when cycleStack3 => updateFlag := true;
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when cycleStack4 => updateFlag := true;
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when cycleRead => if opcInfo(opcRti) = '1' then
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when cycleStack2 =>
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updateFlag := true;
|
||||
when cycleStack3 =>
|
||||
updateFlag := true;
|
||||
when cycleStack4 =>
|
||||
updateFlag := true;
|
||||
when cycleRead =>
|
||||
if opcInfo(opcRti) = '1' then
|
||||
updateFlag := true;
|
||||
end if;
|
||||
when cycleWrite => if opcInfo(opcStackData) = '1' then
|
||||
when cycleWrite =>
|
||||
if opcInfo(opcStackData) = '1' then
|
||||
updateFlag := true;
|
||||
end if;
|
||||
when others => null;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
|
||||
if updateFlag then
|
||||
|
|
@ -1301,32 +1337,35 @@ calcT: process(clk)
|
|||
-- -----------------------------------------------------------------------
|
||||
-- Data out
|
||||
-- -----------------------------------------------------------------------
|
||||
calcDo: process(clk)
|
||||
calcDo: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if enable = '1' then
|
||||
doReg <= aluRmwOut;
|
||||
case nextCpuCycle is
|
||||
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then
|
||||
when cycleStack2 =>
|
||||
if opcInfo(opcIRQ) = '1' and irqActive = '0' then
|
||||
doReg <= myAddrIncr(15 downto 8);
|
||||
else
|
||||
doReg <= PC(15 downto 8);
|
||||
end if;
|
||||
when cycleStack3 => doReg <= PC(7 downto 0);
|
||||
when cycleRmw => doReg <= di; -- Read-modify-write write old value first.
|
||||
when others => null;
|
||||
when cycleStack3 =>
|
||||
doReg <= PC(7 downto 0);
|
||||
when cycleRmw =>
|
||||
doReg <= di; -- Read-modify-write write old value first.
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
do <= doReg;
|
||||
|
||||
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Write enable
|
||||
-- -----------------------------------------------------------------------
|
||||
calcWe: process(clk)
|
||||
calcWe: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if enable = '1' then
|
||||
|
|
@ -1340,36 +1379,43 @@ calcWe: process(clk)
|
|||
if opcInfo(opcStackUp) = '0' then
|
||||
theWe <= '0';
|
||||
end if;
|
||||
when cycleRmw => theWe <= '0';
|
||||
when cycleWrite => theWe <= '0';
|
||||
when others => null;
|
||||
when cycleRmw =>
|
||||
theWe <= '0';
|
||||
when cycleWrite =>
|
||||
theWe <= '0';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
--nwe <= theWe;
|
||||
--nwe <= theWe;
|
||||
end process;
|
||||
nwe <= theWe;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Program counter
|
||||
-- -----------------------------------------------------------------------
|
||||
calcPC: process(clk)
|
||||
calcPC: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if enable = '1' then
|
||||
case theCpuCycle is
|
||||
when opcodeFetch => PC <= myAddr;
|
||||
when cycle2 => if irqActive = '0' then
|
||||
when opcodeFetch =>
|
||||
PC <= myAddr;
|
||||
when cycle2 =>
|
||||
if irqActive = '0' then
|
||||
if opcInfo(opcSecondByte) = '1' then
|
||||
PC <= myAddrIncr;
|
||||
else
|
||||
PC <= myAddr;
|
||||
end if;
|
||||
end if;
|
||||
when cycle3 => if opcInfo(opcAbsolute) = '1' then
|
||||
when cycle3 =>
|
||||
if opcInfo(opcAbsolute) = '1' then
|
||||
PC <= myAddrIncr;
|
||||
end if;
|
||||
when others => null;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
|
@ -1379,11 +1425,12 @@ calcPC: process(clk)
|
|||
-- -----------------------------------------------------------------------
|
||||
-- Address generation
|
||||
-- -----------------------------------------------------------------------
|
||||
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
|
||||
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
|
||||
begin
|
||||
nextAddr <= nextAddrIncr;
|
||||
case theCpuCycle is
|
||||
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
|
||||
when cycle2 =>
|
||||
if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
|
||||
nextAddr <= nextAddrStack;
|
||||
elsif opcInfo(opcAbsolute) = '1' then
|
||||
nextAddr <= nextAddrIncr;
|
||||
|
|
@ -1396,68 +1443,73 @@ calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
|
|||
else
|
||||
nextAddr <= nextAddrHold;
|
||||
end if;
|
||||
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
|
||||
when cycle3 =>
|
||||
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
|
||||
nextAddr <= nextAddrAbs;
|
||||
else
|
||||
nextAddr <= nextAddrAbsIndexed;
|
||||
end if;
|
||||
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed;
|
||||
when cycleIndirect => nextAddr <= nextAddrIncrL;
|
||||
when cycleBranchTaken => nextAddr <= nextAddrRelative;
|
||||
when cycleBranchPage => if T(7) = '0' then
|
||||
when cyclePreIndirect =>
|
||||
nextAddr <= nextAddrZPIndexed;
|
||||
when cycleIndirect =>
|
||||
nextAddr <= nextAddrIncrL;
|
||||
when cycleBranchTaken =>
|
||||
nextAddr <= nextAddrRelative;
|
||||
when cycleBranchPage =>
|
||||
if T(7) = '0' then
|
||||
nextAddr <= nextAddrIncrH;
|
||||
else
|
||||
nextAddr <= nextAddrDecrH;
|
||||
end if;
|
||||
when cyclePreRead => nextAddr <= nextAddrZPIndexed;
|
||||
when cycleRead => nextAddr <= nextAddrPc;
|
||||
when cyclePreRead =>
|
||||
nextAddr <= nextAddrZPIndexed;
|
||||
when cycleRead =>
|
||||
nextAddr <= nextAddrPc;
|
||||
if opcInfo(opcJump) = '1' then
|
||||
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
|
||||
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
|
||||
nextAddr <= nextAddrIncr;
|
||||
--nextAddr <= nextAddrIncrL;
|
||||
elsif indexOut(8) = '1' then
|
||||
nextAddr <= nextAddrIncrH;
|
||||
elsif opcInfo(opcRmw) = '1' then
|
||||
nextAddr <= nextAddrHold;
|
||||
end if;
|
||||
when cycleRead2 => nextAddr <= nextAddrPc;
|
||||
when cycleRead2 =>
|
||||
nextAddr <= nextAddrPc;
|
||||
if opcInfo(opcRmw) = '1' then
|
||||
nextAddr <= nextAddrHold;
|
||||
end if;
|
||||
when cycleRmw => nextAddr <= nextAddrHold;
|
||||
when cyclePreWrite => nextAddr <= nextAddrHold;
|
||||
when cycleRmw =>
|
||||
nextAddr <= nextAddrHold;
|
||||
when cyclePreWrite =>
|
||||
nextAddr <= nextAddrHold;
|
||||
if opcInfo(opcZeroPage) = '1' then
|
||||
nextAddr <= nextAddrZPIndexed;
|
||||
elsif indexOut(8) = '1' then
|
||||
nextAddr <= nextAddrIncrH;
|
||||
end if;
|
||||
when cycleWrite => nextAddr <= nextAddrPc;
|
||||
when cycleStack1 => nextAddr <= nextAddrStack;
|
||||
when cycleStack2 => nextAddr <= nextAddrStack;
|
||||
when cycleStack3 => nextAddr <= nextAddrStack;
|
||||
when cycleWrite =>
|
||||
nextAddr <= nextAddrPc;
|
||||
when cycleStack1 =>
|
||||
nextAddr <= nextAddrStack;
|
||||
when cycleStack2 =>
|
||||
nextAddr <= nextAddrStack;
|
||||
when cycleStack3 =>
|
||||
nextAddr <= nextAddrStack;
|
||||
if opcInfo(opcStackData) = '0' then
|
||||
nextAddr <= nextAddrPc;
|
||||
end if;
|
||||
when cycleStack4 => nextAddr <= nextAddrIrq;
|
||||
when cycleJump => nextAddr <= nextAddrAbs;
|
||||
|
||||
|
||||
when others => null;
|
||||
when cycleStack4 =>
|
||||
nextAddr <= nextAddrIrq;
|
||||
when cycleJump =>
|
||||
nextAddr <= nextAddrAbs;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
|
||||
if reset = '0' then
|
||||
nextAddr <= nextAddrReset;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
indexAlu: process(opcInfo, myAddr, T, X, Y)
|
||||
indexAlu: process(opcInfo, myAddr, T, X, Y)
|
||||
begin
|
||||
if opcInfo(indexX) = '1' then
|
||||
indexOut <= (B"0" & T) + (B"0" & X);
|
||||
|
|
@ -1470,33 +1522,46 @@ indexAlu: process(opcInfo, myAddr, T, X, Y)
|
|||
end if;
|
||||
end process;
|
||||
|
||||
calcAddr: process(clk)
|
||||
calcAddr: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if enable = '1' then
|
||||
case nextAddr is
|
||||
when nextAddrIncr => myAddr <= myAddrIncr;
|
||||
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
|
||||
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
|
||||
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
|
||||
when nextAddrPc => myAddr <= PC;
|
||||
when nextAddrIrq =>myAddr <= X"FFFE";
|
||||
when nextAddrIncr =>
|
||||
myAddr <= myAddrIncr;
|
||||
when nextAddrIncrL =>
|
||||
myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
|
||||
when nextAddrIncrH =>
|
||||
myAddr(15 downto 8) <= myAddrIncrH;
|
||||
when nextAddrDecrH =>
|
||||
myAddr(15 downto 8) <= myAddrDecrH;
|
||||
when nextAddrPc =>
|
||||
myAddr <= PC;
|
||||
when nextAddrIrq =>
|
||||
myAddr <= X"FFFE";
|
||||
if nmiReg = '0' then
|
||||
myAddr <= X"FFFA";
|
||||
end if;
|
||||
when nextAddrReset => myAddr <= X"FFFC";
|
||||
when nextAddrAbs => myAddr <= di & T;
|
||||
when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0);
|
||||
when nextAddrReset =>
|
||||
myAddr <= X"FFFC";
|
||||
when nextAddrAbs =>
|
||||
myAddr <= di & T;
|
||||
when nextAddrAbsIndexed =>
|
||||
if theOpcode = x"7C" then
|
||||
myAddr <= (di & T) + (x"00"& X);
|
||||
else
|
||||
myAddr <= di & indexOut(7 downto 0);
|
||||
end if;
|
||||
when nextAddrZeroPage => myAddr <= "00000000" & di;
|
||||
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
|
||||
when nextAddrStack => myAddr <= "00000001" & S;
|
||||
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
|
||||
when others => null;
|
||||
when nextAddrZeroPage =>
|
||||
myAddr <= "00000000" & di;
|
||||
when nextAddrZPIndexed =>
|
||||
myAddr <= "00000000" & indexOut(7 downto 0);
|
||||
when nextAddrStack =>
|
||||
myAddr <= "00000001" & S;
|
||||
when nextAddrRelative =>
|
||||
myAddr(7 downto 0) <= indexOut(7 downto 0);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
|
@ -1511,11 +1576,12 @@ calcAddr: process(clk)
|
|||
--
|
||||
-- calcsync: process(clk)
|
||||
-- begin
|
||||
--
|
||||
-- if enable = '1' then
|
||||
-- case theCpuCycle is
|
||||
-- when opcodeFetch => sync <= '1';
|
||||
-- when others => sync <= '0';
|
||||
-- when opcodeFetch =>
|
||||
-- sync <= '1';
|
||||
-- when others =>
|
||||
-- sync <= '0';
|
||||
-- end case;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user