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Updated to use 65C02 core

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Change-Id: Ieb458e48d3dc42cee08a9f03237271f101d105b7
This commit is contained in:
David Banks 2015-06-19 12:08:38 +01:00
parent fc0993c9fb
commit 8a81b56304
3 changed files with 72 additions and 30 deletions
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6
AtomCpuMon.xise
View File

@ -20,7 +20,7 @@
</file>
<file xil_pn:name="src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@ -257,6 +257,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="src/AlanD/R65Cx2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>

30
src/AlanD/R65Cx2.vhd
View File

@ -26,8 +26,9 @@ entity R65C02 is
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
@ -847,15 +848,16 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
end if;
when others => null;
end case;
if rising_edge(clk) then
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
end if;
-- end if;
end process;
@ -909,12 +911,13 @@ calcNextOpcode: process(clk, di, reset, processIrq)
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
process(clk)
begin
if rising_edge(clk) then
-- DMB Remove Pipelining
-- process(clk)
-- begin
-- if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
end if;
end process;
-- end if;
-- end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
@ -1511,6 +1514,13 @@ calcAddr: process(clk)
end process;
sync_irq <= irqActive;
Regs <= std_logic_vector(PC) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;

66
src/AtomCpuMon.vhd
View File

@ -23,6 +23,10 @@ use work.OhoPack.all ;
entity AtomCpuMon is
generic (
UseT65Core : boolean := false;
UseAlanDCore : boolean := true
);
port (
clock49 : in std_logic;
@ -76,7 +80,10 @@ architecture behavioral of AtomCpuMon is
signal Addr_int : std_logic_vector(15 downto 0);
signal IRQ_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal cpu_addr_us: unsigned (15 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal Phi0_a : std_logic;
signal Phi0_b : std_logic;
signal Phi0_c : std_logic;
@ -124,24 +131,45 @@ begin
DataIn => memory_din
);
cpu_t65 : entity work.T65 port map (
mode => "00",
Abort_n => '1',
SO_n => SO_n,
Res_n => Res_n,
Enable => Rdy_int,
Clk => cpu_clk,
Rdy => '1',
IRQ_n => IRQ_n_sync,
NMI_n => NMI_n_sync,
R_W_n => R_W_n_int,
Sync => Sync_int,
A(23 downto 16) => open,
A(15 downto 0) => Addr_int,
DI => Din,
DO => Dout,
Regs => Regs
);
GenT65Core: if UseT65Core generate
inst_t65: entity work.T65 port map (
mode => "00",
Abort_n => '1',
SO_n => SO_n,
Res_n => Res_n,
Enable => Rdy_int,
Clk => cpu_clk,
Rdy => '1',
IRQ_n => IRQ_n_sync,
NMI_n => NMI_n_sync,
R_W_n => R_W_n_int,
Sync => Sync_int,
A(23 downto 16) => open,
A(15 downto 0) => Addr_int,
DI => Din,
DO => Dout,
Regs => Regs
);
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map (
reset => RES_n,
clk => cpu_clk,
enable => Rdy_int,
nmi_n => NMI_n_sync,
irq_n => IRQ_n_sync,
di => unsigned(Din),
do => cpu_dout_us,
addr => cpu_addr_us,
nwe => R_W_n_int,
sync => Sync_int,
sync_irq => open,
Regs => Regs
);
Dout <= std_logic_vector(cpu_dout_us);
Addr_int <= std_logic_vector(cpu_addr_us);
end generate;
sync_gen : process(cpu_clk, Res_n)
begin