mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-01-23 12:30:03 +00:00
Improvements to the multi-platform build scripts
Change-Id: I403d566a3f022451d41f158b499a25941b2c7e0d
This commit is contained in:
parent
5410c32db3
commit
92680588cb
@ -262,7 +262,7 @@
|
|||||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
@ -286,7 +286,7 @@
|
|||||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
@ -290,7 +290,7 @@
|
|||||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
@ -266,7 +266,7 @@
|
|||||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
@ -286,7 +286,7 @@
|
|||||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
|
34
gen_mcs.sh
Executable file
34
gen_mcs.sh
Executable file
@ -0,0 +1,34 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
|
||||||
|
DESIGNS="6502cpu 6502fast 6502mon z80cpu 6809cpu"
|
||||||
|
DATE=$(date +"%Y%m%d_%H%M")
|
||||||
|
|
||||||
|
VERSION=$(grep "define VERSION" firmware/AtomBusMon.c | cut -d\" -f2)
|
||||||
|
|
||||||
|
DIR=releases/$VERSION/$DATE
|
||||||
|
|
||||||
|
mkdir -p $DIR
|
||||||
|
|
||||||
|
pushd firmware
|
||||||
|
|
||||||
|
# Compile the firmware and inject into the .bit file
|
||||||
|
for i in $DESIGNS
|
||||||
|
do
|
||||||
|
make -f Makefile.$i clean
|
||||||
|
make -f Makefile.$i
|
||||||
|
done
|
||||||
|
|
||||||
|
# Create a .MCS file and move to releases directory
|
||||||
|
. /opt/Xilinx/14.7/ISE_DS/settings*.sh
|
||||||
|
for i in $DESIGNS
|
||||||
|
do
|
||||||
|
NAME=avr${i}
|
||||||
|
promgen -u 0 $NAME.bit -o $NAME.mcs -p mcs -w -spi -s 8192
|
||||||
|
mv $NAME.mcs ../$DIR
|
||||||
|
rm -f $NAME.bit $NAME.cfi $NAME.prm
|
||||||
|
done
|
||||||
|
|
||||||
|
popd
|
||||||
|
|
||||||
|
ls -lt $DIR
|
||||||
|
|
@ -1,6 +1,23 @@
|
|||||||
#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
|
#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
|
||||||
|
|
||||||
|
project open AtomBusMon.xise
|
||||||
|
process run "Generate Programming File"
|
||||||
|
project close
|
||||||
|
|
||||||
project open AtomCpuMon.xise
|
project open AtomCpuMon.xise
|
||||||
process run "Generate Programming File"
|
process run "Generate Programming File"
|
||||||
project close
|
project close
|
||||||
exit
|
|
||||||
|
|
||||||
|
project open AtomFast6502.xise
|
||||||
|
process run "Generate Programming File"
|
||||||
|
project close
|
||||||
|
|
||||||
|
project open Z80CpuMon.xise
|
||||||
|
process run "Generate Programming File"
|
||||||
|
project close
|
||||||
|
|
||||||
|
project open MC6809ECpuMon.xise
|
||||||
|
process run "Generate Programming File"
|
||||||
|
project close
|
||||||
|
|
||||||
|
exit
|
||||||
|
@ -1,5 +1,23 @@
|
|||||||
#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
|
#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
|
||||||
|
|
||||||
|
project open AtomBusMon.xise
|
||||||
|
project clean
|
||||||
|
project close
|
||||||
|
|
||||||
project open AtomCpuMon.xise
|
project open AtomCpuMon.xise
|
||||||
project clean
|
project clean
|
||||||
project close
|
project close
|
||||||
|
|
||||||
|
project open AtomFast6502.xise
|
||||||
|
project clean
|
||||||
|
project close
|
||||||
|
|
||||||
|
project open Z80CpuMon.xise
|
||||||
|
project clean
|
||||||
|
project close
|
||||||
|
|
||||||
|
project open MC6809ECpuMon.xise
|
||||||
|
project clean
|
||||||
|
project close
|
||||||
|
|
||||||
exit
|
exit
|
||||||
|
Loading…
x
Reference in New Issue
Block a user