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6502: Remove superfluous done state

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Change-Id: Ieaab323c1d2e553c6636d86ebb31dde4948a0c21
This commit is contained in:
David Banks 2019-11-03 13:22:25 +00:00
parent bcd1937d3d
commit 973047db77
1 changed files with 7 additions and 8 deletions
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15
src/MOS6502CpuMonCore.vhd
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@ -74,7 +74,7 @@ end MOS6502CpuMonCore;
architecture behavioral of MOS6502CpuMonCore is
type state_type is (idle, nop0, nop1, rd, wr, done);
type state_type is (idle, nop0, nop1, rd, wr);
signal state : state_type;
@ -298,12 +298,9 @@ begin
state <= nop0;
-- rd is a monitor initiated read cycle
when rd =>
state <= done;
-- rd is a monitor initiated read cycle
state <= nop0;
-- wr is a monitor initiated write cycle
when wr =>
state <= done;
-- done is a dead cycle, provides extra address hold time after a reas of write
when done =>
state <= nop0;
end case;
end if;
@ -319,7 +316,7 @@ begin
'1';
Addr <= Addr_int(15 downto 0) when state = idle else
memory_addr when state = rd or state = wr or state = done else
memory_addr when state = rd or state = wr else
(others => '0');
Sync <= Sync_int when state = idle else
@ -329,7 +326,9 @@ begin
Dout <= Dout_int when state = idle else
memory_dout;
memory_done <= '1' when state = done else '0';
-- Data is captured by the bus monitor on the rising edge of cpu_clk
-- that sees done = 1.
memory_done <= '1' when state = rd or state = wr else '0';
memory_din <= Din;