From 9cd63d78aa99d29c8385f5582c2a5822c90110fd Mon Sep 17 00:00:00 2001 From: David Banks Date: Wed, 26 Nov 2025 09:07:49 +0000 Subject: [PATCH] Altera: Use Altera WatchEvents from BeebFPGA (which has fwft set) Change-Id: I9ad3d0c09099b83c115a405f7837b117581fbeef --- src/{DCM/DCM0Altera.vhd => altera/DCM0.vhd} | 0 src/altera/WatchEvents_CycloneIV.vhd | 155 ++++++++++++++++++++ target/ep4ce6e22c/ice6809/WatchEvents.vhd | 81 ---------- target/ep4ce6e22c/ice6809/ice6809.qsf | 5 +- 4 files changed, 158 insertions(+), 83 deletions(-) rename src/{DCM/DCM0Altera.vhd => altera/DCM0.vhd} (100%) create mode 100644 src/altera/WatchEvents_CycloneIV.vhd delete mode 100644 target/ep4ce6e22c/ice6809/WatchEvents.vhd diff --git a/src/DCM/DCM0Altera.vhd b/src/altera/DCM0.vhd similarity index 100% rename from src/DCM/DCM0Altera.vhd rename to src/altera/DCM0.vhd diff --git a/src/altera/WatchEvents_CycloneIV.vhd b/src/altera/WatchEvents_CycloneIV.vhd new file mode 100644 index 0000000..8e3115e --- /dev/null +++ b/src/altera/WatchEvents_CycloneIV.vhd @@ -0,0 +1,155 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY WatchEvents IS + PORT + ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END WatchEvents; + + +ARCHITECTURE SYN OF watchevents IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0); + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (71 DOWNTO 0); + rdreq : IN STD_LOGIC ; + sclr : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0); + wrreq : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + empty <= sub_wire0; + full <= sub_wire1; + dout <= sub_wire2(71 DOWNTO 0); + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone IV", + lpm_numwords => 512, + lpm_showahead => "ON", + lpm_type => "scfifo", + lpm_width => 72, + lpm_widthu => 9, + overflow_checking => "ON", + underflow_checking => "ON", + use_eab => "ON" + ) + PORT MAP ( + clock => clk, + data => din, + rdreq => rd_en, + sclr => srst, + wrreq => wr_en, + empty => sub_wire0, + full => sub_wire1, + q => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "512" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "0" +-- Retrieval info: PRIVATE: Width NUMERIC "72" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "72" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]" +-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +-- Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]" +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr" +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WatchEvents_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/target/ep4ce6e22c/ice6809/WatchEvents.vhd b/target/ep4ce6e22c/ice6809/WatchEvents.vhd deleted file mode 100644 index bd4fd88..0000000 --- a/target/ep4ce6e22c/ice6809/WatchEvents.vhd +++ /dev/null @@ -1,81 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY WatchEvents IS - PORT - ( - clk : IN STD_LOGIC ; - din : IN STD_LOGIC_VECTOR (71 DOWNTO 0); - rd_en : IN STD_LOGIC ; - wr_en : IN STD_LOGIC ; - srst : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - dout : OUT STD_LOGIC_VECTOR (71 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) - ); -END WatchEvents; - - -ARCHITECTURE SYN OF watchevents IS - - SIGNAL sub_wire0 : STD_LOGIC ; - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC_VECTOR (71 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (8 DOWNTO 0); - - COMPONENT scfifo - GENERIC ( - add_ram_output_register : STRING; - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - overflow_checking : STRING; - underflow_checking : STRING; - use_eab : STRING - ); - PORT ( - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (71 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - - scfifo_component : scfifo - GENERIC MAP ( - add_ram_output_register => "OFF", - intended_device_family => "Cyclone IV E", - lpm_numwords => 512, - lpm_showahead => "OFF", - lpm_type => "scfifo", - lpm_width => 72, - lpm_widthu => 9, - overflow_checking => "ON", - underflow_checking => "ON", - use_eab => "ON" - ) - PORT MAP ( - clock => clk, - data => din, - rdreq => rd_en, - wrreq => wr_en, - empty => empty, - full => full, - q => dout, - usedw => open - ); - -END SYN; diff --git a/target/ep4ce6e22c/ice6809/ice6809.qsf b/target/ep4ce6e22c/ice6809/ice6809.qsf index 2f21496..e38b4fb 100644 --- a/target/ep4ce6e22c/ice6809/ice6809.qsf +++ b/target/ep4ce6e22c/ice6809/ice6809.qsf @@ -91,13 +91,13 @@ set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ExtIRQ_Controller.vhd set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/RAMDataReg.vhd set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd -set_global_assignment -name VHDL_FILE ../../../src/DCM/DCM0Altera.vhd +set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd +set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMonCycloneIV.vhd set_global_assignment -name VHDL_FILE ../../../src/MC6809CpuMon.vhd set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd set_global_assignment -name VHDL_FILE ../../../src/SYS09/cpu09l.vhd -set_global_assignment -name VHDL_FILE WatchEvents.vhd set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -112,6 +112,7 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_24 -to clock