From 9d0e74b94e1787396875d8085e3cb17ab483bcc7 Mon Sep 17 00:00:00 2001 From: David Banks Date: Thu, 17 Oct 2019 11:25:32 +0100 Subject: [PATCH] 6502/65C02: Add power up reset generation (AlanD 65C02 core needs this) Change-Id: I8e24d0f724dc353be296546815462feba8dffc4b --- firmware/AtomBusMon.c | 2 +- src/MOS6502CpuMonCore.vhd | 29 ++++++++++++++++++++++++----- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/firmware/AtomBusMon.c b/firmware/AtomBusMon.c index 350c668..7711e2d 100644 --- a/firmware/AtomBusMon.c +++ b/firmware/AtomBusMon.c @@ -10,7 +10,7 @@ * VERSION and NAME are used in the start-up message ********************************************************/ -#define VERSION "0.80" +#define VERSION "0.81" #if defined(CPU_Z80) #define NAME "ICE-Z80" diff --git a/src/MOS6502CpuMonCore.vhd b/src/MOS6502CpuMonCore.vhd index 21c7a0c..af8d72f 100644 --- a/src/MOS6502CpuMonCore.vhd +++ b/src/MOS6502CpuMonCore.vhd @@ -84,8 +84,10 @@ architecture behavioral of MOS6502CpuMonCore is signal hold : std_logic; signal Addr_int : std_logic_vector(23 downto 0); - signal cpu_addr_us: unsigned (15 downto 0); - signal cpu_dout_us: unsigned (7 downto 0); + signal cpu_addr_us : unsigned (15 downto 0); + signal cpu_dout_us : unsigned (7 downto 0); + signal cpu_reset_n : std_logic; + signal reset_counter : std_logic_vector(9 downto 0); signal Regs : std_logic_vector(63 downto 0); signal Regs1 : std_logic_vector(255 downto 0); @@ -195,12 +197,30 @@ begin cpu_clken_ss <= (not hold) and cpu_clken; + -- Generate a short (~1ms @ 1MHz) power up reset pulse + -- + -- This is in case FPGA configuration takes longer than + -- the length of the host system reset pulse. + -- + -- Some 6502 cores (particularly the AlanD core) needs + -- reset to be asserted to start. + + process(cpu_clk) + begin + if rising_edge(cpu_clk) then + if (reset_counter(reset_counter'high) = '0') then + reset_counter <= reset_counter + 1; + end if; + cpu_reset_n <= Res_n_in and reset_counter(reset_counter'high); + end if; + end process; + GenT65Core: if UseT65Core generate inst_t65: entity work.T65 port map ( mode => "00", Abort_n => '1', SO_n => SO_n, - Res_n => Res_n_in, + Res_n => cpu_reset_n, Enable => cpu_clken_ss, Clk => cpu_clk, Rdy => '1', @@ -217,7 +237,7 @@ begin GenAlanDCore: if UseAlanDCore generate inst_r65c02: entity work.r65c02 port map ( - reset => Res_n_in, + reset => cpu_reset_n, clk => cpu_clk, enable => cpu_clken_ss, nmi_n => NMI_n_masked, @@ -234,7 +254,6 @@ begin Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us); end generate; - -- This block generates a hold signal that acts as the inverse of a clock enable -- for the CPU. See comments above for why this is a cycle delayed a cycle. hold_gen : process(cpu_clk)