From a4aa6df31a55215def290a0abf06359425cfaf43 Mon Sep 17 00:00:00 2001 From: David Banks Date: Tue, 1 Aug 2017 09:25:12 +0100 Subject: [PATCH] Added new top level generics to 6502 and 6809 designs Change-Id: I14d70471b97948c165210bebad88b60965531207 --- src/AtomBusMon.vhd | 19 ++++++++++++++----- src/AtomCpuMon.vhd | 19 ++++++++++++++----- src/AtomFast6502.vhd | 19 ++++++++++++++----- src/MC6809ECpuMon.vhd | 19 ++++++++++++++----- 4 files changed, 56 insertions(+), 20 deletions(-) diff --git a/src/AtomBusMon.vhd b/src/AtomBusMon.vhd index f50e593..50e4887 100644 --- a/src/AtomBusMon.vhd +++ b/src/AtomBusMon.vhd @@ -24,7 +24,10 @@ entity AtomBusMon is generic ( LEDsActiveHigh : boolean := false; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL - SW2ActiveHigh : boolean := false -- default value correct for GODIL + SW2ActiveHigh : boolean := false; -- default value correct for GODIL + ClkMult : integer := 10; -- default value correct for GODIL + ClkDiv : integer := 31; -- default value correct for GODIL + ClkPer : real := 20.345 -- default value correct for GODIL ); port ( clock49 : in std_logic; @@ -88,10 +91,16 @@ begin led6 <= not led6_n when LEDsActiveHigh else led6_n; led8 <= not led8_n when LEDsActiveHigh else led8_n; - inst_dcm0 : entity work.DCM0 port map( - CLKIN_IN => clock49, - CLKFX_OUT => clock_avr - ); + inst_dcm0 : entity work.DCM0 + generic map ( + ClkMult => ClkMult, + ClkDiv => ClkDiv, + ClkPer => ClkPer + ) + port map( + CLKIN_IN => clock49, + CLKFX_OUT => clock_avr + ); mon : entity work.BusMonCore generic map ( diff --git a/src/AtomCpuMon.vhd b/src/AtomCpuMon.vhd index 5f4f1c8..faefbd2 100644 --- a/src/AtomCpuMon.vhd +++ b/src/AtomCpuMon.vhd @@ -28,7 +28,10 @@ entity AtomCpuMon is UseAlanDCore : boolean := false; LEDsActiveHigh : boolean := false; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL - SW2ActiveHigh : boolean := false -- default value correct for GODIL + SW2ActiveHigh : boolean := false; -- default value correct for GODIL + ClkMult : integer := 10; -- default value correct for GODIL + ClkDiv : integer := 31; -- default value correct for GODIL + ClkPer : real := 20.345 -- default value correct for GODIL ); port ( clock49 : in std_logic; @@ -111,10 +114,16 @@ begin led6 <= not led6_n when LEDsActiveHigh else led6_n; led8 <= not led8_n when LEDsActiveHigh else led8_n; - inst_dcm0 : entity work.DCM0 port map( - CLKIN_IN => clock49, - CLKFX_OUT => clock_avr - ); + inst_dcm0 : entity work.DCM0 + generic map ( + ClkMult => ClkMult, + ClkDiv => ClkDiv, + ClkPer => ClkPer + ) + port map( + CLKIN_IN => clock49, + CLKFX_OUT => clock_avr + ); core : entity work.MOS6502CpuMonCore generic map ( diff --git a/src/AtomFast6502.vhd b/src/AtomFast6502.vhd index 356fae4..4901d0e 100644 --- a/src/AtomFast6502.vhd +++ b/src/AtomFast6502.vhd @@ -43,7 +43,10 @@ entity AtomFast6502 is UseAlanDCore : boolean := false; LEDsActiveHigh : boolean := false; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL - SW2ActiveHigh : boolean := false -- default value correct for GODIL + SW2ActiveHigh : boolean := false; -- default value correct for GODIL + ClkMult : integer := 10; -- default value correct for GODIL + ClkDiv : integer := 31; -- default value correct for GODIL + ClkPer : real := 20.345 -- default value correct for GODIL ); port ( clock49 : in std_logic; @@ -136,10 +139,16 @@ begin led6 <= not led6_n when LEDsActiveHigh else led6_n; led8 <= not led8_n when LEDsActiveHigh else led8_n; - inst_dcm0 : entity work.DCM0 port map( - CLKIN_IN => clock49, - CLKFX_OUT => clock_avr - ); + inst_dcm0 : entity work.DCM0 + generic map ( + ClkMult => ClkMult, + ClkDiv => ClkDiv, + ClkPer => ClkPer + ) + port map( + CLKIN_IN => clock49, + CLKFX_OUT => clock_avr + ); inst_dcm2 : entity work.DCM2 port map( CLKIN_IN => Phi0, diff --git a/src/MC6809ECpuMon.vhd b/src/MC6809ECpuMon.vhd index 6e1571d..c5eb075 100644 --- a/src/MC6809ECpuMon.vhd +++ b/src/MC6809ECpuMon.vhd @@ -26,7 +26,10 @@ entity MC6809ECpuMon is UseCPU09Core : boolean := true; LEDsActiveHigh : boolean := false; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL - SW2ActiveHigh : boolean := false -- default value correct for GODIL + SW2ActiveHigh : boolean := false; -- default value correct for GODIL + ClkMult : integer := 10; -- default value correct for GODIL + ClkDiv : integer := 31; -- default value correct for GODIL + ClkPer : real := 20.345 -- default value correct for GODIL ); port ( clock49 : in std_logic; @@ -168,10 +171,16 @@ begin led6 <= not led6_n when LEDsActiveHigh else led6_n; led8 <= not led8_n when LEDsActiveHigh else led8_n; - inst_dcm0 : entity work.DCM0 port map( - CLKIN_IN => clock49, - CLKFX_OUT => clock_avr - ); + inst_dcm0 : entity work.DCM0 + generic map ( + ClkMult => ClkMult, + ClkDiv => ClkDiv, + ClkPer => ClkPer + ) + port map( + CLKIN_IN => clock49, + CLKFX_OUT => clock_avr + ); mon : entity work.BusMonCore generic map (