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Z80: give a tad more address delay time (Acorn 2nd Proc issue)
Change-Id: I4872f8cc25d68978e856610ca7abaf4a12520028
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@ -89,7 +89,7 @@ end Z80CpuMon;
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architecture behavioral of Z80CpuMon is
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architecture behavioral of Z80CpuMon is
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type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3);
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type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3);
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signal state : state_type;
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signal state : state_type;
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@ -101,6 +101,8 @@ type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa,
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signal busmon_clk : std_logic;
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signal busmon_clk : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Addr_int : std_logic_vector(15 downto 0);
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-- signal Addr1 : std_logic_vector(15 downto 0);
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-- signal Addr2 : std_logic_vector(15 downto 0);
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signal RD_n_int : std_logic;
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signal RD_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal MREQ_n_int : std_logic;
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signal MREQ_n_int : std_logic;
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@ -417,17 +419,36 @@ begin
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-- TODO: Also need to take account of BUSRQ_n/BUSAK_n
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-- TODO: Also need to take account of BUSRQ_n/BUSAK_n
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MREQ_n <= MREQ_n_int when state = idle or state = resume else mon_mreq_n and mon_xx_n;
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MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n and mon_xx_n;
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IORQ_n <= IORQ_n_int when state = idle or state = resume else mon_iorq_n;
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IORQ_n <= IORQ_n_int when state = idle else mon_iorq_n;
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RFSH_n <= RFSH_n_int when state = idle or state = resume else mon_rfsh_n;
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RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n;
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WR_n <= WR_n_int when state = idle or state = resume else mon_wr_n;
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WR_n <= WR_n_int when state = idle else mon_wr_n;
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RD_n <= RD_n_int when state = idle or state = resume else mon_rd_n and mon_xx_n;
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RD_n <= RD_n_int when state = idle else mon_rd_n and mon_xx_n;
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M1_n <= M1_n_int when state = idle or state = resume else mon_m1_n;
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M1_n <= M1_n_int when state = idle else mon_m1_n;
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Addr <= Addr_int when state = idle or state = resume else
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Addr <= x"0000" when state = nop_t1 or state = nop_t2 else
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x"0000" when state = nop_t1 or state = nop_t2 else
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rfsh_addr when state = nop_t3 or state = nop_t4 else
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rfsh_addr when state = nop_t3 or state = nop_t4 else
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memory_addr;
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memory_addr when state /= idle else
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Addr_int;
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-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
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-- and MREQ being released at the start of T3. Otherwise, the ROM switching
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-- during NMI doesn't work reliably due to glitches. See:
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-- https://stardot.org.uk/forums/viewtopic.php?p=212096#p212096
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--
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-- Reordering the above Addr expression so Addr_int is last instead of
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-- first seems to fix the issue, but is clearly very dependent on how the Xilinx
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-- tools route the design.
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--
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-- If the problem recurs, we should switch to something like:
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--
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-- addr_delay : process(clock49)
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-- begin
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-- if rising_edge(clock49) then
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-- Addr2 <= Addr1;
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-- Addr <= Addr2;
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-- end if;
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-- end process;
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Data <= memory_dout when state = wr_wa or state = wr_t2 or state = wr_t3 else
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Data <= memory_dout when state = wr_wa or state = wr_t2 or state = wr_t3 else
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Dout when state = idle and Den = '1' else
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Dout when state = idle and Den = '1' else
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@ -529,10 +550,6 @@ begin
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mon_m1_n <= mode;
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mon_m1_n <= mode;
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end if;
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end if;
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-- Resume,
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when resume =>
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state <= idle;
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-- Read cycle
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-- Read cycle
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when rd_t1 =>
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when rd_t1 =>
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if io_not_mem = '1' then
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if io_not_mem = '1' then
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