From b4402844ae74ac6ba686f31dcafcda05924fa1e2 Mon Sep 17 00:00:00 2001
From: David Banks <dave@hoglet.com>
Date: Thu, 17 Oct 2019 15:55:49 +0100
Subject: [PATCH] 6502/65c02: Implement Rdy internally

Change-Id: I0ddc55cf7d4674c68760f7ad53fcea7d07629f8b
---
 src/AtomCpuMon.vhd        | 25 ++++++++++++++++++++++++-
 src/MOS6502CpuMonCore.vhd |  2 +-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/src/AtomCpuMon.vhd b/src/AtomCpuMon.vhd
index 6ab1e3b..6aaa552 100644
--- a/src/AtomCpuMon.vhd
+++ b/src/AtomCpuMon.vhd
@@ -83,6 +83,8 @@ architecture behavioral of AtomCpuMon is
     signal Din           : std_logic_vector(7 downto 0);
     signal Dout          : std_logic_vector(7 downto 0);
 
+    signal Rdy_latched   : std_logic;
+
     signal IRQ_n_sync    : std_logic;
     signal NMI_n_sync    : std_logic;
 
@@ -147,7 +149,7 @@ begin
         SO_n         => SO_n,
         Res_n_in     => Res_n_in,
         Res_n_out    => Res_n_out,
-        Rdy          => Rdy,
+        Rdy          => Rdy_latched,
         trig         => trig,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
@@ -173,6 +175,27 @@ begin
         end if;
     end process;
 
+    -- 6502: Sample Rdy on the rising edge of Phi0
+    rdy_6502: if UseT65Core generate
+        process(Phi0)
+        begin
+            if rising_edge(Phi0) then
+                Rdy_latched <= Rdy;
+            end if;
+        end process;
+    end generate;
+
+    -- 65C02: Sample Rdy on the falling edge of Phi0
+    rdy_65c02: if UseAlanDCore generate
+        process(Phi0)
+        begin
+            if falling_edge(Phi0) then
+                Rdy_latched <= Rdy;
+            end if;
+        end process;
+    end generate;
+
+    -- Sample Data on the falling edge of Phi0_a
     data_latch : process(Phi0_a)
     begin
         if falling_edge(Phi0_a) then
diff --git a/src/MOS6502CpuMonCore.vhd b/src/MOS6502CpuMonCore.vhd
index af8d72f..a614c61 100644
--- a/src/MOS6502CpuMonCore.vhd
+++ b/src/MOS6502CpuMonCore.vhd
@@ -195,7 +195,7 @@ begin
     Regs1( 63 downto 48) <= last_PC;
     Regs1(255 downto 64) <= (others => '0');
 
-    cpu_clken_ss <= (not hold) and cpu_clken;
+    cpu_clken_ss <= Rdy and (not hold) and cpu_clken;
 
     -- Generate a short (~1ms @ 1MHz) power up reset pulse
     --