diff --git a/target/lx9_dave/ice6502/Makefile b/target/lx9_dave/ice6502/Makefile new file mode 100644 index 0000000..218d489 --- /dev/null +++ b/target/lx9_dave/ice6502/Makefile @@ -0,0 +1,18 @@ +# The root directory of the project +ROOT = ../../.. + +# The common directory for makefile includes, etc. +COMMON = ../../common + +# The project .bit file produced by the Xilinx .xise project +PROJECT = AtomCpuMon + +# The target .bit file to be generated including the monitor program +TARGET = ice6502 + +# Frequuency that the AVR runs at +F_CPU = 19354838 + +# Common include files +include $(COMMON)/Makefile_$(TARGET).inc +include $(COMMON)/Makefile.inc diff --git a/target/lx9_dave/ice6502/board.ucf b/target/lx9_dave/ice6502/board.ucf new file mode 100644 index 0000000..31359a3 --- /dev/null +++ b/target/lx9_dave/ice6502/board.ucf @@ -0,0 +1,81 @@ +NET "clock49" TNM_NET = clk_period_grp_49; +TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.00ns HIGH; + +NET "Phi0" TNM_NET = clk_period_grp_phi0; +TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW; + +NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "clock49" LOC="P21" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator + +#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1 +#NET "Rdy" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2 +NET "Phi1" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3 +NET "IRQ_n" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4 +#NET "NC" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5 +NET "NMI_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6 +NET "Sync" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7 +#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8 +NET "Addr<0>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9 +NET "Addr<1>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10 +NET "Addr<2>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11 +NET "Addr<3>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12 +NET "Addr<4>" LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13 +NET "Addr<5>" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14 +NET "Addr<6>" LOC="P55" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15 +NET "Addr<7>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16 +NET "Addr<8>" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17 +NET "Addr<9>" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18 +NET "Addr<10>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19 +NET "Addr<11>" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20 + +#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21 +NET "Addr<12>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22 +NET "Addr<13>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23 +NET "Addr<14>" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24 +NET "Addr<15>" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25 +NET "Data<7>" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26 +NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27 +NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28 +NET "Data<4>" LOC="P75" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29 +NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30 +NET "Data<2>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31 +NET "Data<1>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32 +NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33 +NET "R_W_n" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34 +#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35 +#NET "NC" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36 +NET "Phi0" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37 +NET "SO_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38 +NET "Phi2" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39 +NET "Res_n" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40 + + +# LEDs and Switches +NET "led3" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active +NET "led6" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active +NET "led8" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint +NET "sw1" LOC="P133" | IOSTANDARD = LVCMOS33 ; # reset +NET "sw2" LOC="P132" | IOSTANDARD = LVCMOS33 ; # interrupt + +# 7-segment LED +NET tmosi LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET tdin LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET tcclk LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; + +# UART +NET "avr_TxD" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "avr_RxD" LOC="P23" | IOSTANDARD = LVCMOS33 ; + +# External trigger inputs +NET "trig<0>" LOC="P134" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P137" | IOSTANDARD = LVCMOS33 ; + +# Jumpers +NET "fakeTube_n" LOC="P27" | IOSTANDARD = LVCMOS33 ; + + + + + + diff --git a/target/lx9_dave/ice6502/ice6502.xise b/target/lx9_dave/ice6502/ice6502.xise new file mode 100644 index 0000000..a6008b7 --- /dev/null +++ b/target/lx9_dave/ice6502/ice6502.xise @@ -0,0 +1,622 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/lx9_dave/ice6502/memory.bmm b/target/lx9_dave/ice6502/memory.bmm new file mode 100644 index 0000000..7acc1c1 --- /dev/null +++ b/target/lx9_dave/ice6502/memory.bmm @@ -0,0 +1,38 @@ +ADDRESS_MAP avrmap PPC405 0 + + ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff] + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0]; + END_BUS_BLOCK; + + END_ADDRESS_SPACE; + +END_ADDRESS_MAP; \ No newline at end of file diff --git a/target/lx9_dave/icez80/Makefile b/target/lx9_dave/icez80/Makefile new file mode 100644 index 0000000..abfec3a --- /dev/null +++ b/target/lx9_dave/icez80/Makefile @@ -0,0 +1,18 @@ +# The root directory of the project +ROOT = ../../.. + +# The common directory for makefile includes, etc. +COMMON = ../../common + +# The project .bit file produced by the Xilinx .xise project +PROJECT = Z80CpuMon + +# The target .bit file to be generated including the monitor program +TARGET = icez80 + +# Frequuency that the AVR runs at +F_CPU = 19354838 + +# Common include files +include $(COMMON)/Makefile_$(TARGET).inc +include $(COMMON)/Makefile.inc diff --git a/target/lx9_dave/icez80/board.ucf b/target/lx9_dave/icez80/board.ucf new file mode 100644 index 0000000..686c29a --- /dev/null +++ b/target/lx9_dave/icez80/board.ucf @@ -0,0 +1,76 @@ + +NET "CLK_n" TNM_NET = clk_period_grp_clk_n; +TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 250ns LOW; + +NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "clock49" LOC="P21" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator + +NET "Addr<11>" LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1 +NET "Addr<12>" LOC="P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2 +NET "Addr<13>" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3 +NET "Addr<14>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4 +NET "Addr<15>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5 +NET "CLK_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6 +NET "Data<4>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7 +NET "Data<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8 +NET "Data<5>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9 +NET "Data<6>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10 +#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11 +NET "Data<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12 +NET "Data<7>" LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13 +NET "Data<0>" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14 +NET "Data<1>" LOC="P55" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15 +NET "INT_n" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16 +NET "NMI_n" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17 +NET "HALT_n" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18 +NET "MREQ_n" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19 +NET "IORQ_n" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20 + +NET "RD_n" LOC="P75" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21 +NET "WR_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22 +NET "BUSAK_n" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23 +NET "WAIT_n" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24 +NET "BUSRQ_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25 +NET "RESET_n" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26 +NET "M1_n" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27 +NET "RFSH_n" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28 +#NET "GND" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29 +NET "Addr<0>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30 +NET "Addr<1>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31 +NET "Addr<2>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32 +NET "Addr<3>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33 +NET "Addr<4>" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34 +NET "Addr<5>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35 +NET "Addr<6>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36 +NET "Addr<7>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37 +NET "Addr<8>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38 +NET "Addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39 +NET "Addr<10>" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40 + +# LEDs and Switches +NET "led3" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active +NET "led6" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active +NET "led8" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint +NET "sw1" LOC="P133" | IOSTANDARD = LVCMOS33 ; # reset +NET "sw2" LOC="P132" | IOSTANDARD = LVCMOS33 ; # interrupt + +# 7-segment LED +NET tmosi LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET tdin LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET tcclk LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; + +# UART +NET "avr_TxD" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "avr_RxD" LOC="P23" | IOSTANDARD = LVCMOS33 ; + +# External trigger inputs +NET "trig<0>" LOC="P134" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P137" | IOSTANDARD = LVCMOS33 ; + +# Test outputs +NET "test1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test2" LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test3" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "test4" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test5" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; diff --git a/target/lx9_dave/icez80/icez80.xise b/target/lx9_dave/icez80/icez80.xise new file mode 100644 index 0000000..ae59a2c --- /dev/null +++ b/target/lx9_dave/icez80/icez80.xise @@ -0,0 +1,616 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/lx9_dave/icez80/memory.bmm b/target/lx9_dave/icez80/memory.bmm new file mode 100644 index 0000000..13098d9 --- /dev/null +++ b/target/lx9_dave/icez80/memory.bmm @@ -0,0 +1,42 @@ +ADDRESS_MAP avrmap PPC405 0 + + ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff] + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0]; + END_BUS_BLOCK; + + BUS_BLOCK + mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0]; + END_BUS_BLOCK; + + END_ADDRESS_SPACE; + +END_ADDRESS_MAP; \ No newline at end of file diff --git a/target/lx9_dave/ipcore/WatchEvents.ngc b/target/lx9_dave/ipcore/WatchEvents.ngc new file mode 100644 index 0000000..6abc4b0 --- /dev/null +++ b/target/lx9_dave/ipcore/WatchEvents.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/target/lx9_dave/ipcore/WatchEvents.vhd b/target/lx9_dave/ipcore/WatchEvents.vhd new file mode 100644 index 0000000..4afc294 --- /dev/null +++ b/target/lx9_dave/ipcore/WatchEvents.vhd @@ -0,0 +1,280 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2017 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file WatchEvents.vhd when simulating +-- the core, WatchEvents. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY WatchEvents IS + PORT ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END WatchEvents; + +ARCHITECTURE WatchEvents_a OF WatchEvents IS +-- synthesis translate_off +COMPONENT wrapped_WatchEvents + PORT ( + clk : IN STD_LOGIC; + srst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral) + GENERIC MAP ( + c_add_ngc_constraint => 0, + c_application_type_axis => 0, + c_application_type_rach => 0, + c_application_type_rdch => 0, + c_application_type_wach => 0, + c_application_type_wdch => 0, + c_application_type_wrch => 0, + c_axi_addr_width => 32, + c_axi_aruser_width => 1, + c_axi_awuser_width => 1, + c_axi_buser_width => 1, + c_axi_data_width => 64, + c_axi_id_width => 4, + c_axi_ruser_width => 1, + c_axi_type => 0, + c_axi_wuser_width => 1, + c_axis_tdata_width => 64, + c_axis_tdest_width => 4, + c_axis_tid_width => 8, + c_axis_tkeep_width => 4, + c_axis_tstrb_width => 4, + c_axis_tuser_width => 4, + c_axis_type => 0, + c_common_clock => 1, + c_count_type => 0, + c_data_count_width => 10, + c_default_value => "BlankString", + c_din_width => 72, + c_din_width_axis => 1, + c_din_width_rach => 32, + c_din_width_rdch => 64, + c_din_width_wach => 32, + c_din_width_wdch => 64, + c_din_width_wrch => 2, + c_dout_rst_val => "0", + c_dout_width => 72, + c_enable_rlocs => 0, + c_enable_rst_sync => 1, + c_error_injection_type => 0, + c_error_injection_type_axis => 0, + c_error_injection_type_rach => 0, + c_error_injection_type_rdch => 0, + c_error_injection_type_wach => 0, + c_error_injection_type_wdch => 0, + c_error_injection_type_wrch => 0, + c_family => "spartan6", + c_full_flags_rst_val => 0, + c_has_almost_empty => 0, + c_has_almost_full => 0, + c_has_axi_aruser => 0, + c_has_axi_awuser => 0, + c_has_axi_buser => 0, + c_has_axi_rd_channel => 0, + c_has_axi_ruser => 0, + c_has_axi_wr_channel => 0, + c_has_axi_wuser => 0, + c_has_axis_tdata => 0, + c_has_axis_tdest => 0, + c_has_axis_tid => 0, + c_has_axis_tkeep => 0, + c_has_axis_tlast => 0, + c_has_axis_tready => 1, + c_has_axis_tstrb => 0, + c_has_axis_tuser => 0, + c_has_backup => 0, + c_has_data_count => 0, + c_has_data_counts_axis => 0, + c_has_data_counts_rach => 0, + c_has_data_counts_rdch => 0, + c_has_data_counts_wach => 0, + c_has_data_counts_wdch => 0, + c_has_data_counts_wrch => 0, + c_has_int_clk => 0, + c_has_master_ce => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_has_prog_flags_axis => 0, + c_has_prog_flags_rach => 0, + c_has_prog_flags_rdch => 0, + c_has_prog_flags_wach => 0, + c_has_prog_flags_wdch => 0, + c_has_prog_flags_wrch => 0, + c_has_rd_data_count => 0, + c_has_rd_rst => 0, + c_has_rst => 0, + c_has_slave_ce => 0, + c_has_srst => 1, + c_has_underflow => 0, + c_has_valid => 0, + c_has_wr_ack => 0, + c_has_wr_data_count => 0, + c_has_wr_rst => 0, + c_implementation_type => 0, + c_implementation_type_axis => 1, + c_implementation_type_rach => 1, + c_implementation_type_rdch => 1, + c_implementation_type_wach => 1, + c_implementation_type_wdch => 1, + c_implementation_type_wrch => 1, + c_init_wr_pntr_val => 0, + c_interface_type => 0, + c_memory_type => 1, + c_mif_file_name => "BlankString", + c_msgon_val => 1, + c_optimization_mode => 0, + c_overflow_low => 0, + c_preload_latency => 0, + c_preload_regs => 1, + c_prim_fifo_type => "512x72", + c_prog_empty_thresh_assert_val => 4, + c_prog_empty_thresh_assert_val_axis => 1022, + c_prog_empty_thresh_assert_val_rach => 1022, + c_prog_empty_thresh_assert_val_rdch => 1022, + c_prog_empty_thresh_assert_val_wach => 1022, + c_prog_empty_thresh_assert_val_wdch => 1022, + c_prog_empty_thresh_assert_val_wrch => 1022, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_type => 0, + c_prog_empty_type_axis => 0, + c_prog_empty_type_rach => 0, + c_prog_empty_type_rdch => 0, + c_prog_empty_type_wach => 0, + c_prog_empty_type_wdch => 0, + c_prog_empty_type_wrch => 0, + c_prog_full_thresh_assert_val => 511, + c_prog_full_thresh_assert_val_axis => 1023, + c_prog_full_thresh_assert_val_rach => 1023, + c_prog_full_thresh_assert_val_rdch => 1023, + c_prog_full_thresh_assert_val_wach => 1023, + c_prog_full_thresh_assert_val_wdch => 1023, + c_prog_full_thresh_assert_val_wrch => 1023, + c_prog_full_thresh_negate_val => 510, + c_prog_full_type => 0, + c_prog_full_type_axis => 0, + c_prog_full_type_rach => 0, + c_prog_full_type_rdch => 0, + c_prog_full_type_wach => 0, + c_prog_full_type_wdch => 0, + c_prog_full_type_wrch => 0, + c_rach_type => 0, + c_rd_data_count_width => 10, + c_rd_depth => 512, + c_rd_freq => 1, + c_rd_pntr_width => 9, + c_rdch_type => 0, + c_reg_slice_mode_axis => 0, + c_reg_slice_mode_rach => 0, + c_reg_slice_mode_rdch => 0, + c_reg_slice_mode_wach => 0, + c_reg_slice_mode_wdch => 0, + c_reg_slice_mode_wrch => 0, + c_synchronizer_stage => 2, + c_underflow_low => 0, + c_use_common_overflow => 0, + c_use_common_underflow => 0, + c_use_default_settings => 0, + c_use_dout_rst => 1, + c_use_ecc => 0, + c_use_ecc_axis => 0, + c_use_ecc_rach => 0, + c_use_ecc_rdch => 0, + c_use_ecc_wach => 0, + c_use_ecc_wdch => 0, + c_use_ecc_wrch => 0, + c_use_embedded_reg => 0, + c_use_fifo16_flags => 0, + c_use_fwft_data_count => 1, + c_valid_low => 0, + c_wach_type => 0, + c_wdch_type => 0, + c_wr_ack_low => 0, + c_wr_data_count_width => 10, + c_wr_depth => 512, + c_wr_depth_axis => 1024, + c_wr_depth_rach => 16, + c_wr_depth_rdch => 1024, + c_wr_depth_wach => 16, + c_wr_depth_wdch => 1024, + c_wr_depth_wrch => 16, + c_wr_freq => 1, + c_wr_pntr_width => 9, + c_wr_pntr_width_axis => 10, + c_wr_pntr_width_rach => 4, + c_wr_pntr_width_rdch => 10, + c_wr_pntr_width_wach => 4, + c_wr_pntr_width_wdch => 10, + c_wr_pntr_width_wrch => 4, + c_wr_response_latency => 1, + c_wrch_type => 0 + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_WatchEvents + PORT MAP ( + clk => clk, + srst => srst, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty + ); +-- synthesis translate_on + +END WatchEvents_a; diff --git a/target/lx9_dave/ipcore/WatchEvents.xco b/target/lx9_dave/ipcore/WatchEvents.xco new file mode 100644 index 0000000..c9d8b3f --- /dev/null +++ b/target/lx9_dave/ipcore/WatchEvents.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jul 25 16:17:25 2017 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=WatchEvents +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Common_Clock_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=511 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=510 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=512 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Synchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 3745e82a diff --git a/target/lx9_dave/ipcore/WatchEvents.xise b/target/lx9_dave/ipcore/WatchEvents.xise new file mode 100644 index 0000000..ca7715e --- /dev/null +++ b/target/lx9_dave/ipcore/WatchEvents.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +