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AtomBusMon
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Make commands 6-bits, add Special and TimerMode commands 

Change-Id: I8862fba0cf4c1e54ee831a547bf3337bbe7cf973
This commit is contained in:
David Banks 2020-06-21 14:12:33 +01:00
parent ddc2ff358c
commit c0275ff059
26 changed files with 223 additions and 103 deletions
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143
firmware/AtomBusMon.c
View File

@ -87,7 +87,8 @@ char *cmdStrings[] = {
"watcho",
#endif
"clear",
"trigger"
"trigger",
"timermode"
};
// Must be kept in step with cmdStrings (just above)
@ -140,7 +141,8 @@ void (*cmdFuncs[])(char *params) = {
doCmdWatchWrIO,
#endif
doCmdClear,
doCmdTrigger
doCmdTrigger,
doCmdTimerMode
};
#if defined(EXTENDED_HELP)
@ -201,7 +203,7 @@ static const uint8_t helpMeta[] PROGMEM = {
8, 13, // compare
22, 1, // mem
26, 2, // rd
41, 3, // wr
42, 3, // wr
#if defined(CPU_Z80)
20, 1, // io
19, 2, // in
@ -218,22 +220,23 @@ static const uint8_t helpMeta[] PROGMEM = {
31, 7, // srec
30, 14, // special
28, 7, // reset
34, 6, // trace
35, 6, // trace
1, 7, // blist
6, 4, // breakx
40, 4, // watchx
41, 4, // watchx
4, 4, // breakr
38, 4, // watchr
39, 4, // watchr
5, 4, // breakw
39, 4, // watchw
40, 4, // watchw
#if defined(CPU_Z80)
2, 4, // breaki
36, 4, // watchi
37, 4, // watchi
3, 4, // breako
37, 4, // watcho
38, 4, // watcho
#endif
7, 0, // clear
35, 5, // trigger
36, 5, // trigger
34, 14, // timer
0, 0
};
@ -248,42 +251,42 @@ static const uint8_t helpMeta[] PROGMEM = {
#define CTRL_DDR DDRB
#define CTRL_DIN PINB
// A 0->1 transition on bit 5 actually sends a command
#define CMD_EDGE 0x20
// A 0->1 transition on bit 6 actually sends a command
#define CMD_EDGE 0x40
// Commands are placed on bits 4..0
#define CMD_MASK 0x1F
// Bits 7..6 are the special function output bits
// On the 6502, these are used to mask IRQ and NMI
#define SPECIAL_0 6
#define SPECIAL_1 7
#define SPECIAL_MASK ((1<<SPECIAL_0) | (1<<SPECIAL_1))
// Commands are placed on bits 5..0
#define CMD_MASK 0x3F
// Hardware Commands:
//
// 0000x Enable/Disable single strpping
// 0001x Enable/Disable breakpoints / watches
// 0010x Load breakpoint / watch register
// 0011x Reset CPU
// 01000 Singe Step CPU
// 01001 Read FIFO
// 01010 Reset FIFO
// 01011 Unused
// 0110x Load address/data register
// 0111x Unused
// 10000 Read Memory
// 10001 Read Memory and Auto Inc Address
// 10010 Write Memory
// 10011 Write Memory and Auto Inc Address
// 10100 Read IO
// 10101 Read IO and Auto Inc Address
// 10110 Write IO
// 10111 Write IO and Auto Inc Address
// 11000 Exec Go
// 11xx1 Unused
// 11x1x Unused
// 111xx Unused
// 00000x Enable/Disable single strpping
// 00001x Enable/Disable breakpoints / watches
// 00010x Load breakpoint / watch register
// 00011x Reset CPU
// 001000 Singe Step CPU
// 001001 Read FIFO
// 001010 Reset FIFO
// 001011 Unused
// 00110x Load address/data register
// 00111x Unused
// 010000 Read Memory
// 010001 Read Memory and Auto Inc Address
// 010010 Write Memory
// 010011 Write Memory and Auto Inc Address
// 010100 Read IO
// 010101 Read IO and Auto Inc Address
// 010110 Write IO
// 010111 Write IO and Auto Inc Address
// 011000 Exec Go
// 011xx1 Unused
// 011x1x Unused
// 0111xx Unused
// 100xxx Special
// 1010xx Timer Mode
// 00 - count cpu cycles where clken = 1 and CountCycle = 1
// 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
// 10 - free running timer, using busmon_clk as the source
// 11 - free running timer, using trig0 as the source
#define CMD_SINGLE_ENABLE 0x00
#define CMD_BRKPT_ENABLE 0x02
@ -302,6 +305,8 @@ static const uint8_t helpMeta[] PROGMEM = {
#define CMD_WR_IO 0x16
#define CMD_WR_IO_INC 0x17
#define CMD_EXEC_GO 0x18
#define CMD_SPECIAL 0x20
#define CMD_TIMER_MODE 0x28
/********************************************************
* AVR Status Register Definitions
@ -474,6 +479,21 @@ static const char *modeStrings[NUM_MODES] = {
MODE10
};
// The number of different timer sources
#define NUM_TIMERS 4
static const char TIMER0[] PROGMEM = "Normal Cycles";
static const char TIMER1[] PROGMEM = "All Cycles";
static const char TIMER2[] PROGMEM = "Internal Timer";
static const char TIMER3[] PROGMEM = "External Timer";
static const char *timerStrings[NUM_TIMERS] = {
TIMER0,
TIMER1,
TIMER2,
TIMER3
};
// For convenience, several masks are defined that group similar types of breakpoint/watch
// Mask for all breakpoint types
@ -605,6 +625,12 @@ uint8_t cmd_id = 0xff;
#define MASK_CLOCK_ERROR 1
#define MASK_TIMEOUT_ERROR 2
// Current special setting
uint8_t special = 0x00;
// Current timer mode setting
uint8_t timer_mode = 0x00;
/********************************************************
* User Command Processor
********************************************************/
@ -1366,7 +1392,7 @@ void helpForCommand(uint8_t i) {
logstr(" ");
logs(cmdStrings[i]);
tmp = strlen(cmdStrings[i]);
while (tmp++ < 9) {
while (tmp++ < 10) {
logc(' ');
}
while ((tmp = pgm_read_byte(ip++))) {
@ -1985,13 +2011,32 @@ void logSpecial(char *function, uint8_t value) {
}
void doCmdSpecial(char *params) {
uint8_t special = 0xff;
parsehex2(params, &special);
if (special <= 3) {
CTRL_PORT = (CTRL_PORT & ~SPECIAL_MASK) | (special << SPECIAL_0);
uint8_t tmp = 0xff;
parsehex2(params, &tmp);
#if defined(CPU_6809)
if (tmp <= 7) {
#else
if (tmp <= 3) {
#endif
special = tmp;
hwCmd(CMD_SPECIAL, special);
}
logSpecial("NMI", CTRL_PORT & (1 << SPECIAL_1));
logSpecial("IRQ", CTRL_PORT & (1 << SPECIAL_0));
#if defined(CPU_6809)
logSpecial("FIRQ", special & 4);
#endif
logSpecial("NMI", special & 2);
logSpecial("IRQ", special & 1);
}
void doCmdTimerMode(char *params) {
uint8_t tmp = 0xff;
parsehex2(params, &tmp);
if (tmp <= NUM_TIMERS) {
timer_mode = tmp;
hwCmd(CMD_TIMER_MODE, timer_mode);
}
logpgmstr(timerStrings[timer_mode]);
logstr("\n");
}
void doCmdTrace(char *params) {

1
firmware/AtomBusMon.h
View File

@ -77,6 +77,7 @@ void doCmdTest(char *params);
void doCmdSave(char *params);
void doCmdSRec(char *params);
void doCmdSpecial(char *params);
void doCmdTimerMode(char *params);
void doCmdTrace(char *params);
void doCmdTrigger(char *params);
void doCmdWatchI(char *params);

134
src/BusMonCore.vhd
View File

@ -72,7 +72,7 @@ entity BusMonCore is
Done : in std_logic;
-- Special outputs (function is CPU specific)
Special : out std_logic_vector(1 downto 0);
Special : out std_logic_vector(2 downto 0);
-- Single Step interface
SS_Single : out std_logic;
@ -124,15 +124,18 @@ architecture behavioral of BusMonCore is
signal cmd_ack : std_logic;
signal cmd_ack1 : std_logic;
signal cmd_ack2 : std_logic;
signal cmd : std_logic_vector(4 downto 0);
signal cmd : std_logic_vector(5 downto 0);
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Data1 : std_logic_vector(7 downto 0);
signal ext_clk : std_logic;
signal timer0Count : std_logic_vector(23 downto 0);
signal timer1Count : std_logic_vector(23 downto 0);
signal cycleCount : std_logic_vector(23 downto 0);
signal cycleCount_inst : std_logic_vector(23 downto 0);
signal instrCount : std_logic_vector(23 downto 0);
signal single : std_logic;
signal reset : std_logic;
@ -181,6 +184,8 @@ architecture behavioral of BusMonCore is
signal dropped_counter : std_logic_vector(3 downto 0);
signal timer_mode : std_logic_vector(1 downto 0);
begin
inst_oho_dy1 : entity work.Oho_Dy1 port map (
@ -224,9 +229,9 @@ begin
portbout(2) => cmd(2),
portbout(3) => cmd(3),
portbout(4) => cmd(4),
portbout(5) => cmd_edge,
portbout(6) => Special(0),
portbout(7) => Special(1),
portbout(5) => cmd(5),
portbout(6) => cmd_edge,
portbout(7) => open,
-- Status Port
portdin(0) => '0',
@ -289,7 +294,7 @@ begin
-- DataWr1 is the data being written delayed by 1 cycle
-- DataRd is the data being read, that is already one cycle late
-- bw_state1(1) is 1 for writes, and 0 for reads
fifo_din <= cycleCount_inst & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
-- Implement a 4-bit saturating counter of the number of dropped events
process (busmon_clk)
@ -325,9 +330,9 @@ begin
mux <= addr_inst(7 downto 0) when muxsel = 0 else
addr_inst(15 downto 8) when muxsel = 1 else
din_reg when muxsel = 2 else
cycleCount(23 downto 16) when muxsel = 3 else
cycleCount(7 downto 0) when muxsel = 4 else
cycleCount(15 downto 8) when muxsel = 5 else
instrCount(23 downto 16) when muxsel = 3 else
instrCount(7 downto 0) when muxsel = 4 else
instrCount(15 downto 8) when muxsel = 5 else
fifo_dout(7 downto 0) when muxsel = 6 else
fifo_dout(15 downto 8) when muxsel = 7 else
@ -432,40 +437,55 @@ begin
end process;
-- CPU Control Commands
-- 0000x Enable/Disable single stepping
-- 0001x Enable/Disable breakpoints / watches
-- 0010x Load breakpoint / watch register
-- 0011x Reset CPU
-- 01000 Singe Step CPU
-- 01001 Read FIFO
-- 01010 Reset FIFO
-- 01011 Unused
-- 0110x Load address/data register
-- 0111x Unused
-- 10000 Read Memory
-- 10001 Read Memory and Auto Inc Address
-- 10010 Write Memory
-- 10011 Write Memory and Auto Inc Address
-- 10100 Read IO
-- 10101 Read IO and Auto Inc Address
-- 10110 Write IO
-- 10111 Write IO and Auto Inc Address
-- 11000 Execute 6502 instruction
-- 111xx Unused
-- 11x1x Unused
-- 11xx1 Unused
-- 00000x Enable/Disable single stepping
-- 00001x Enable/Disable breakpoints / watches
-- 00010x Load breakpoint / watch register
-- 00011x Reset CPU
-- 001000 Singe Step CPU
-- 001001 Read FIFO
-- 001010 Reset FIFO
-- 001011 Unused
-- 00110x Load address/data register
-- 00111x Unused
-- 010000 Read Memory
-- 010001 Read Memory and Auto Inc Address
-- 010010 Write Memory
-- 010011 Write Memory and Auto Inc Address
-- 010100 Read IO
-- 010101 Read IO and Auto Inc Address
-- 010110 Write IO
-- 010111 Write IO and Auto Inc Address
-- 011000 Execute 6502 instruction
-- 0111xx Unused
-- 011x1x Unused
-- 011xx1 Unused
-- 100xxx Special
-- 1010xx Timer Mode
-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
-- 10 - free running timer, using busmon_clk as the source
-- 11 - free running timer, using trig0 as the source
-- Use trig0 to drive a free running counter for absolute timings
ext_clk <= trig(0);
timer1Process: process (ext_clk)
begin
if rising_edge(ext_clk) then
timer1Count <= timer1Count + 1;
end if;
end process;
cpuProcess: process (busmon_clk)
begin
if rising_edge(busmon_clk) then
timer0Count <= timer0Count + 1;
if busmon_clken = '1' then
-- Cycle counter, wraps every 16s at 1MHz
-- Cycle counter
if (cpu_reset_n = '0') then
cycleCount <= (others => '0');
elsif (CountCycle = '1') then
elsif (CountCycle = '1' or timer_mode(0) = '1') then
cycleCount <= cycleCount + 1;
end if;
-- Command processing
cmd_edge1 <= cmd_edge;
cmd_edge2 <= cmd_edge1;
@ -479,60 +499,68 @@ begin
exec <= '0';
SS_Step <= '0';
if (cmd_edge2 /= cmd_edge1) then
if (cmd(4 downto 1) = "0000") then
if (cmd(5 downto 1) = "00000") then
single <= cmd(0);
end if;
if (cmd(4 downto 1) = "0001") then
if (cmd(5 downto 1) = "00001") then
brkpt_enable <= cmd(0);
end if;
if (cmd(4 downto 1) = "0010") then
if (cmd(5 downto 1) = "00010") then
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
end if;
if (cmd(4 downto 1) = "0110") then
if (cmd(5 downto 1) = "00110") then
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
end if;
if (cmd(4 downto 1) = "0011") then
if (cmd(5 downto 1) = "00011") then
reset <= cmd(0);
end if;
if (cmd(4 downto 0) = "01001") then
if (cmd(5 downto 0) = "01001") then
fifo_rd <= '1';
end if;
if (cmd(4 downto 0) = "01010") then
if (cmd(5 downto 0) = "01010") then
fifo_rst <= '1';
end if;
if (cmd(4 downto 1) = "1000") then
if (cmd(5 downto 1) = "01000") then
memory_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(4 downto 1) = "1001") then
if (cmd(5 downto 1) = "01001") then
memory_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(4 downto 1) = "1010") then
if (cmd(5 downto 1) = "01010") then
io_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(4 downto 1) = "1011") then
if (cmd(5 downto 1) = "01011") then
io_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(4 downto 0) = "11000") then
if (cmd(5 downto 0) = "011000") then
exec <= '1';
end if;
if (cmd(5 downto 3) = "100") then
Special <= cmd(2 downto 0);
end if;
if (cmd(5 downto 2) = "1010") then
timer_mode <= cmd(1 downto 0);
end if;
-- Acknowlege certain commands immediately
if cmd(4) = '0' then
if cmd(5 downto 4) /= "01" then
cmd_ack <= not cmd_ack;
end if;
@ -552,7 +580,7 @@ begin
single <= '1';
end if;
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "01000")) then
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
Rdy_int <= (not brkpt_active);
SS_Step <= (not brkpt_active);
else
@ -562,7 +590,13 @@ begin
-- Latch instruction address for the whole cycle
if (Sync = '1') then
addr_inst <= Addr;
cycleCount_inst <= cycleCount;
if timer_mode = "10" then
instrCount <= timer0Count;
elsif timer_mode = "11" then
instrCount <= timer1Count;
else
instrCount <= cycleCount;
end if;
end if;
-- Breakpoints and Watches written to the FIFO

4
src/MC6809CpuMon.vhd
View File

@ -124,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(1 downto 0);
signal special : std_logic_vector(2 downto 0);
signal LIC_int : std_logic;
@ -212,8 +212,8 @@ begin
SS_Single => SS_Single
);
FIRQ_n_masked <= FIRQ_n or special(2);
NMI_n_masked <= NMI_n or special(1);
FIRQ_n_masked <= FIRQ_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last

2
src/MOS6502CpuMonCore.vhd
View File

@ -100,7 +100,7 @@ architecture behavioral of MOS6502CpuMonCore is
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(1 downto 0);
signal special : std_logic_vector(2 downto 0);
signal memory_rd : std_logic;
signal memory_rd1 : std_logic;

2
src/Z80CpuMon.vhd
View File

@ -118,7 +118,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(1 downto 0);
signal special : std_logic_vector(2 downto 0);
signal skipNextOpcode : std_logic;
signal Regs : std_logic_vector(255 downto 0);

2
target/godil_250/_icez80/board.ucf
View File

@ -3,6 +3,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1

2
target/godil_250/ice6502/board.ucf
View File

@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2

2
target/godil_250/ice65c02/board.ucf
View File

@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2

2
target/godil_250/ice6809/board.ucf
View File

@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3

2
target/godil_500/ice6502/board.ucf
View File

@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2

2
target/godil_500/ice65c02/board.ucf
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@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2

2
target/godil_500/ice6809/board.ucf
View File

@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3

2
target/godil_500/icez80/board.ucf
View File

@ -5,6 +5,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3

2
target/lx9_dave/ice6502/board.ucf
View File

@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_dave/ice65c02/board.ucf
View File

@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_dave/ice6809/board.ucf
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@ -3,6 +3,8 @@ TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_dave/icez80/board.ucf
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@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW;
NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "Addr<11>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_jason/ice6502/board.ucf
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@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_jason/ice65c02/board.ucf
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@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_jason/ice6809/board.ucf
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@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "IRQ_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

2
target/lx9_jason/icez80/board.ucf
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@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Addr<11>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Addr<13>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

2
target/lx9_jason_flipped/ice6502/board.ucf
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@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_jason_flipped/ice65c02/board.ucf
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@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

2
target/lx9_jason_flipped/ice6809/board.ucf
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@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "NMI_n" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

2
target/lx9_jason_flipped/icez80/board.ucf
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@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "Addr<12>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Addr<13>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3