mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-17 11:29:31 +00:00
Make commands 6-bits, add Special and TimerMode commands
Change-Id: I8862fba0cf4c1e54ee831a547bf3337bbe7cf973
This commit is contained in:
parent
ddc2ff358c
commit
c0275ff059
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@ -87,7 +87,8 @@ char *cmdStrings[] = {
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"watcho",
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"watcho",
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#endif
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#endif
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"clear",
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"clear",
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"trigger"
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"trigger",
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"timermode"
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};
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};
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// Must be kept in step with cmdStrings (just above)
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// Must be kept in step with cmdStrings (just above)
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@ -140,7 +141,8 @@ void (*cmdFuncs[])(char *params) = {
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doCmdWatchWrIO,
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doCmdWatchWrIO,
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#endif
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#endif
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doCmdClear,
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doCmdClear,
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doCmdTrigger
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doCmdTrigger,
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doCmdTimerMode
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};
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};
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#if defined(EXTENDED_HELP)
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#if defined(EXTENDED_HELP)
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@ -201,7 +203,7 @@ static const uint8_t helpMeta[] PROGMEM = {
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8, 13, // compare
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8, 13, // compare
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22, 1, // mem
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22, 1, // mem
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26, 2, // rd
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26, 2, // rd
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41, 3, // wr
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42, 3, // wr
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#if defined(CPU_Z80)
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#if defined(CPU_Z80)
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20, 1, // io
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20, 1, // io
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19, 2, // in
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19, 2, // in
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@ -218,22 +220,23 @@ static const uint8_t helpMeta[] PROGMEM = {
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31, 7, // srec
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31, 7, // srec
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30, 14, // special
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30, 14, // special
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28, 7, // reset
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28, 7, // reset
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34, 6, // trace
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35, 6, // trace
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1, 7, // blist
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1, 7, // blist
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6, 4, // breakx
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6, 4, // breakx
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40, 4, // watchx
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41, 4, // watchx
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4, 4, // breakr
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4, 4, // breakr
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38, 4, // watchr
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39, 4, // watchr
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5, 4, // breakw
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5, 4, // breakw
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39, 4, // watchw
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40, 4, // watchw
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#if defined(CPU_Z80)
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#if defined(CPU_Z80)
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2, 4, // breaki
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2, 4, // breaki
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36, 4, // watchi
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37, 4, // watchi
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3, 4, // breako
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3, 4, // breako
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37, 4, // watcho
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38, 4, // watcho
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#endif
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#endif
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7, 0, // clear
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7, 0, // clear
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35, 5, // trigger
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36, 5, // trigger
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34, 14, // timer
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0, 0
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0, 0
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};
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};
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@ -248,42 +251,42 @@ static const uint8_t helpMeta[] PROGMEM = {
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#define CTRL_DDR DDRB
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#define CTRL_DDR DDRB
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#define CTRL_DIN PINB
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#define CTRL_DIN PINB
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// A 0->1 transition on bit 5 actually sends a command
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// A 0->1 transition on bit 6 actually sends a command
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#define CMD_EDGE 0x20
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#define CMD_EDGE 0x40
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// Commands are placed on bits 4..0
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// Commands are placed on bits 5..0
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#define CMD_MASK 0x1F
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#define CMD_MASK 0x3F
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// Bits 7..6 are the special function output bits
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// On the 6502, these are used to mask IRQ and NMI
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#define SPECIAL_0 6
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#define SPECIAL_1 7
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#define SPECIAL_MASK ((1<<SPECIAL_0) | (1<<SPECIAL_1))
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// Hardware Commands:
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// Hardware Commands:
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//
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//
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// 0000x Enable/Disable single strpping
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// 00000x Enable/Disable single strpping
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// 0001x Enable/Disable breakpoints / watches
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// 00001x Enable/Disable breakpoints / watches
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// 0010x Load breakpoint / watch register
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// 00010x Load breakpoint / watch register
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// 0011x Reset CPU
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// 00011x Reset CPU
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// 01000 Singe Step CPU
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// 001000 Singe Step CPU
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// 01001 Read FIFO
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// 001001 Read FIFO
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// 01010 Reset FIFO
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// 001010 Reset FIFO
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// 01011 Unused
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// 001011 Unused
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// 0110x Load address/data register
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// 00110x Load address/data register
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// 0111x Unused
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// 00111x Unused
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// 10000 Read Memory
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// 010000 Read Memory
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// 10001 Read Memory and Auto Inc Address
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// 010001 Read Memory and Auto Inc Address
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// 10010 Write Memory
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// 010010 Write Memory
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// 10011 Write Memory and Auto Inc Address
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// 010011 Write Memory and Auto Inc Address
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// 10100 Read IO
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// 010100 Read IO
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// 10101 Read IO and Auto Inc Address
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// 010101 Read IO and Auto Inc Address
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// 10110 Write IO
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// 010110 Write IO
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// 10111 Write IO and Auto Inc Address
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// 010111 Write IO and Auto Inc Address
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// 11000 Exec Go
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// 011000 Exec Go
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// 11xx1 Unused
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// 011xx1 Unused
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// 11x1x Unused
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// 011x1x Unused
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// 111xx Unused
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// 0111xx Unused
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// 100xxx Special
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// 1010xx Timer Mode
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// 00 - count cpu cycles where clken = 1 and CountCycle = 1
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// 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
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// 10 - free running timer, using busmon_clk as the source
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// 11 - free running timer, using trig0 as the source
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#define CMD_SINGLE_ENABLE 0x00
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#define CMD_SINGLE_ENABLE 0x00
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#define CMD_BRKPT_ENABLE 0x02
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#define CMD_BRKPT_ENABLE 0x02
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@ -302,6 +305,8 @@ static const uint8_t helpMeta[] PROGMEM = {
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#define CMD_WR_IO 0x16
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#define CMD_WR_IO 0x16
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#define CMD_WR_IO_INC 0x17
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#define CMD_WR_IO_INC 0x17
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#define CMD_EXEC_GO 0x18
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#define CMD_EXEC_GO 0x18
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#define CMD_SPECIAL 0x20
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#define CMD_TIMER_MODE 0x28
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/********************************************************
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/********************************************************
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* AVR Status Register Definitions
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* AVR Status Register Definitions
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@ -474,6 +479,21 @@ static const char *modeStrings[NUM_MODES] = {
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MODE10
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MODE10
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};
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};
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// The number of different timer sources
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#define NUM_TIMERS 4
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static const char TIMER0[] PROGMEM = "Normal Cycles";
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static const char TIMER1[] PROGMEM = "All Cycles";
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static const char TIMER2[] PROGMEM = "Internal Timer";
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static const char TIMER3[] PROGMEM = "External Timer";
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static const char *timerStrings[NUM_TIMERS] = {
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TIMER0,
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TIMER1,
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TIMER2,
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TIMER3
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};
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// For convenience, several masks are defined that group similar types of breakpoint/watch
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// For convenience, several masks are defined that group similar types of breakpoint/watch
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// Mask for all breakpoint types
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// Mask for all breakpoint types
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@ -605,6 +625,12 @@ uint8_t cmd_id = 0xff;
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#define MASK_CLOCK_ERROR 1
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#define MASK_CLOCK_ERROR 1
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#define MASK_TIMEOUT_ERROR 2
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#define MASK_TIMEOUT_ERROR 2
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// Current special setting
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uint8_t special = 0x00;
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// Current timer mode setting
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uint8_t timer_mode = 0x00;
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/********************************************************
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/********************************************************
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* User Command Processor
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* User Command Processor
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********************************************************/
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********************************************************/
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@ -1366,7 +1392,7 @@ void helpForCommand(uint8_t i) {
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logstr(" ");
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logstr(" ");
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logs(cmdStrings[i]);
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logs(cmdStrings[i]);
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tmp = strlen(cmdStrings[i]);
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tmp = strlen(cmdStrings[i]);
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while (tmp++ < 9) {
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while (tmp++ < 10) {
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logc(' ');
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logc(' ');
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}
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}
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while ((tmp = pgm_read_byte(ip++))) {
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while ((tmp = pgm_read_byte(ip++))) {
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@ -1985,13 +2011,32 @@ void logSpecial(char *function, uint8_t value) {
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}
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}
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void doCmdSpecial(char *params) {
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void doCmdSpecial(char *params) {
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uint8_t special = 0xff;
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uint8_t tmp = 0xff;
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parsehex2(params, &special);
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parsehex2(params, &tmp);
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if (special <= 3) {
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#if defined(CPU_6809)
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CTRL_PORT = (CTRL_PORT & ~SPECIAL_MASK) | (special << SPECIAL_0);
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if (tmp <= 7) {
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#else
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if (tmp <= 3) {
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#endif
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special = tmp;
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hwCmd(CMD_SPECIAL, special);
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}
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}
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logSpecial("NMI", CTRL_PORT & (1 << SPECIAL_1));
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#if defined(CPU_6809)
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logSpecial("IRQ", CTRL_PORT & (1 << SPECIAL_0));
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logSpecial("FIRQ", special & 4);
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#endif
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logSpecial("NMI", special & 2);
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logSpecial("IRQ", special & 1);
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}
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void doCmdTimerMode(char *params) {
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uint8_t tmp = 0xff;
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parsehex2(params, &tmp);
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if (tmp <= NUM_TIMERS) {
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timer_mode = tmp;
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hwCmd(CMD_TIMER_MODE, timer_mode);
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}
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logpgmstr(timerStrings[timer_mode]);
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logstr("\n");
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}
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}
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void doCmdTrace(char *params) {
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void doCmdTrace(char *params) {
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@ -77,6 +77,7 @@ void doCmdTest(char *params);
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void doCmdSave(char *params);
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void doCmdSave(char *params);
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void doCmdSRec(char *params);
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void doCmdSRec(char *params);
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void doCmdSpecial(char *params);
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void doCmdSpecial(char *params);
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void doCmdTimerMode(char *params);
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void doCmdTrace(char *params);
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void doCmdTrace(char *params);
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void doCmdTrigger(char *params);
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void doCmdTrigger(char *params);
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void doCmdWatchI(char *params);
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void doCmdWatchI(char *params);
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@ -72,7 +72,7 @@ entity BusMonCore is
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Done : in std_logic;
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Done : in std_logic;
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-- Special outputs (function is CPU specific)
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-- Special outputs (function is CPU specific)
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Special : out std_logic_vector(1 downto 0);
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Special : out std_logic_vector(2 downto 0);
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-- Single Step interface
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-- Single Step interface
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SS_Single : out std_logic;
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SS_Single : out std_logic;
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@ -124,15 +124,18 @@ architecture behavioral of BusMonCore is
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signal cmd_ack : std_logic;
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signal cmd_ack : std_logic;
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signal cmd_ack1 : std_logic;
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signal cmd_ack1 : std_logic;
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signal cmd_ack2 : std_logic;
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signal cmd_ack2 : std_logic;
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signal cmd : std_logic_vector(4 downto 0);
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signal cmd : std_logic_vector(5 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal Data1 : std_logic_vector(7 downto 0);
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signal Data1 : std_logic_vector(7 downto 0);
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signal ext_clk : std_logic;
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signal timer0Count : std_logic_vector(23 downto 0);
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signal timer1Count : std_logic_vector(23 downto 0);
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signal cycleCount : std_logic_vector(23 downto 0);
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signal cycleCount : std_logic_vector(23 downto 0);
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signal cycleCount_inst : std_logic_vector(23 downto 0);
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signal instrCount : std_logic_vector(23 downto 0);
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signal single : std_logic;
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signal single : std_logic;
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signal reset : std_logic;
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signal reset : std_logic;
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@ -181,6 +184,8 @@ architecture behavioral of BusMonCore is
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signal dropped_counter : std_logic_vector(3 downto 0);
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signal dropped_counter : std_logic_vector(3 downto 0);
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signal timer_mode : std_logic_vector(1 downto 0);
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begin
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begin
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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@ -224,9 +229,9 @@ begin
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portbout(2) => cmd(2),
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portbout(2) => cmd(2),
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portbout(3) => cmd(3),
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portbout(3) => cmd(3),
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portbout(4) => cmd(4),
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portbout(4) => cmd(4),
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portbout(5) => cmd_edge,
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portbout(5) => cmd(5),
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portbout(6) => Special(0),
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portbout(6) => cmd_edge,
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portbout(7) => Special(1),
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portbout(7) => open,
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-- Status Port
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-- Status Port
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portdin(0) => '0',
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portdin(0) => '0',
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@ -289,7 +294,7 @@ begin
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-- DataWr1 is the data being written delayed by 1 cycle
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-- DataWr1 is the data being written delayed by 1 cycle
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-- DataRd is the data being read, that is already one cycle late
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-- DataRd is the data being read, that is already one cycle late
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-- bw_state1(1) is 1 for writes, and 0 for reads
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-- bw_state1(1) is 1 for writes, and 0 for reads
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fifo_din <= cycleCount_inst & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
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fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
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-- Implement a 4-bit saturating counter of the number of dropped events
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-- Implement a 4-bit saturating counter of the number of dropped events
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process (busmon_clk)
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process (busmon_clk)
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@ -325,9 +330,9 @@ begin
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mux <= addr_inst(7 downto 0) when muxsel = 0 else
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mux <= addr_inst(7 downto 0) when muxsel = 0 else
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addr_inst(15 downto 8) when muxsel = 1 else
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addr_inst(15 downto 8) when muxsel = 1 else
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din_reg when muxsel = 2 else
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din_reg when muxsel = 2 else
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cycleCount(23 downto 16) when muxsel = 3 else
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instrCount(23 downto 16) when muxsel = 3 else
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cycleCount(7 downto 0) when muxsel = 4 else
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instrCount(7 downto 0) when muxsel = 4 else
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cycleCount(15 downto 8) when muxsel = 5 else
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instrCount(15 downto 8) when muxsel = 5 else
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fifo_dout(7 downto 0) when muxsel = 6 else
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fifo_dout(7 downto 0) when muxsel = 6 else
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fifo_dout(15 downto 8) when muxsel = 7 else
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fifo_dout(15 downto 8) when muxsel = 7 else
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@ -432,40 +437,55 @@ begin
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end process;
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end process;
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-- CPU Control Commands
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-- CPU Control Commands
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-- 0000x Enable/Disable single stepping
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-- 00000x Enable/Disable single stepping
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-- 0001x Enable/Disable breakpoints / watches
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-- 00001x Enable/Disable breakpoints / watches
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-- 0010x Load breakpoint / watch register
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-- 00010x Load breakpoint / watch register
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-- 0011x Reset CPU
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-- 00011x Reset CPU
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-- 01000 Singe Step CPU
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-- 001000 Singe Step CPU
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-- 01001 Read FIFO
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-- 001001 Read FIFO
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-- 01010 Reset FIFO
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-- 001010 Reset FIFO
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-- 01011 Unused
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-- 001011 Unused
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-- 0110x Load address/data register
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-- 00110x Load address/data register
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-- 0111x Unused
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-- 00111x Unused
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-- 10000 Read Memory
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-- 010000 Read Memory
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-- 10001 Read Memory and Auto Inc Address
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-- 010001 Read Memory and Auto Inc Address
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-- 10010 Write Memory
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-- 010010 Write Memory
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-- 10011 Write Memory and Auto Inc Address
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-- 010011 Write Memory and Auto Inc Address
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-- 10100 Read IO
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-- 010100 Read IO
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-- 10101 Read IO and Auto Inc Address
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-- 010101 Read IO and Auto Inc Address
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-- 10110 Write IO
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-- 010110 Write IO
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-- 10111 Write IO and Auto Inc Address
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-- 010111 Write IO and Auto Inc Address
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-- 11000 Execute 6502 instruction
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-- 011000 Execute 6502 instruction
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-- 111xx Unused
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-- 0111xx Unused
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-- 11x1x Unused
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-- 011x1x Unused
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-- 11xx1 Unused
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-- 011xx1 Unused
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-- 100xxx Special
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-- 1010xx Timer Mode
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-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
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-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
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-- 10 - free running timer, using busmon_clk as the source
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-- 11 - free running timer, using trig0 as the source
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-- Use trig0 to drive a free running counter for absolute timings
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ext_clk <= trig(0);
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timer1Process: process (ext_clk)
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begin
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if rising_edge(ext_clk) then
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timer1Count <= timer1Count + 1;
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end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
cpuProcess: process (busmon_clk)
|
cpuProcess: process (busmon_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(busmon_clk) then
|
if rising_edge(busmon_clk) then
|
||||||
|
timer0Count <= timer0Count + 1;
|
||||||
if busmon_clken = '1' then
|
if busmon_clken = '1' then
|
||||||
-- Cycle counter, wraps every 16s at 1MHz
|
-- Cycle counter
|
||||||
if (cpu_reset_n = '0') then
|
if (cpu_reset_n = '0') then
|
||||||
cycleCount <= (others => '0');
|
cycleCount <= (others => '0');
|
||||||
elsif (CountCycle = '1') then
|
elsif (CountCycle = '1' or timer_mode(0) = '1') then
|
||||||
cycleCount <= cycleCount + 1;
|
cycleCount <= cycleCount + 1;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
-- Command processing
|
-- Command processing
|
||||||
cmd_edge1 <= cmd_edge;
|
cmd_edge1 <= cmd_edge;
|
||||||
cmd_edge2 <= cmd_edge1;
|
cmd_edge2 <= cmd_edge1;
|
||||||
|
@ -479,60 +499,68 @@ begin
|
||||||
exec <= '0';
|
exec <= '0';
|
||||||
SS_Step <= '0';
|
SS_Step <= '0';
|
||||||
if (cmd_edge2 /= cmd_edge1) then
|
if (cmd_edge2 /= cmd_edge1) then
|
||||||
if (cmd(4 downto 1) = "0000") then
|
if (cmd(5 downto 1) = "00000") then
|
||||||
single <= cmd(0);
|
single <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "0001") then
|
if (cmd(5 downto 1) = "00001") then
|
||||||
brkpt_enable <= cmd(0);
|
brkpt_enable <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "0010") then
|
if (cmd(5 downto 1) = "00010") then
|
||||||
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
|
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "0110") then
|
if (cmd(5 downto 1) = "00110") then
|
||||||
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
|
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "0011") then
|
if (cmd(5 downto 1) = "00011") then
|
||||||
reset <= cmd(0);
|
reset <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 0) = "01001") then
|
if (cmd(5 downto 0) = "01001") then
|
||||||
fifo_rd <= '1';
|
fifo_rd <= '1';
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 0) = "01010") then
|
if (cmd(5 downto 0) = "01010") then
|
||||||
fifo_rst <= '1';
|
fifo_rst <= '1';
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "1000") then
|
if (cmd(5 downto 1) = "01000") then
|
||||||
memory_rd <= '1';
|
memory_rd <= '1';
|
||||||
auto_inc <= cmd(0);
|
auto_inc <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "1001") then
|
if (cmd(5 downto 1) = "01001") then
|
||||||
memory_wr <= '1';
|
memory_wr <= '1';
|
||||||
auto_inc <= cmd(0);
|
auto_inc <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "1010") then
|
if (cmd(5 downto 1) = "01010") then
|
||||||
io_rd <= '1';
|
io_rd <= '1';
|
||||||
auto_inc <= cmd(0);
|
auto_inc <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 1) = "1011") then
|
if (cmd(5 downto 1) = "01011") then
|
||||||
io_wr <= '1';
|
io_wr <= '1';
|
||||||
auto_inc <= cmd(0);
|
auto_inc <= cmd(0);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (cmd(4 downto 0) = "11000") then
|
if (cmd(5 downto 0) = "011000") then
|
||||||
exec <= '1';
|
exec <= '1';
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
|
if (cmd(5 downto 3) = "100") then
|
||||||
|
Special <= cmd(2 downto 0);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
if (cmd(5 downto 2) = "1010") then
|
||||||
|
timer_mode <= cmd(1 downto 0);
|
||||||
|
end if;
|
||||||
|
|
||||||
-- Acknowlege certain commands immediately
|
-- Acknowlege certain commands immediately
|
||||||
if cmd(4) = '0' then
|
if cmd(5 downto 4) /= "01" then
|
||||||
cmd_ack <= not cmd_ack;
|
cmd_ack <= not cmd_ack;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
|
@ -552,7 +580,7 @@ begin
|
||||||
single <= '1';
|
single <= '1';
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "01000")) then
|
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
|
||||||
Rdy_int <= (not brkpt_active);
|
Rdy_int <= (not brkpt_active);
|
||||||
SS_Step <= (not brkpt_active);
|
SS_Step <= (not brkpt_active);
|
||||||
else
|
else
|
||||||
|
@ -562,7 +590,13 @@ begin
|
||||||
-- Latch instruction address for the whole cycle
|
-- Latch instruction address for the whole cycle
|
||||||
if (Sync = '1') then
|
if (Sync = '1') then
|
||||||
addr_inst <= Addr;
|
addr_inst <= Addr;
|
||||||
cycleCount_inst <= cycleCount;
|
if timer_mode = "10" then
|
||||||
|
instrCount <= timer0Count;
|
||||||
|
elsif timer_mode = "11" then
|
||||||
|
instrCount <= timer1Count;
|
||||||
|
else
|
||||||
|
instrCount <= cycleCount;
|
||||||
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
-- Breakpoints and Watches written to the FIFO
|
-- Breakpoints and Watches written to the FIFO
|
||||||
|
|
|
@ -124,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
|
||||||
signal SS_Single : std_logic;
|
signal SS_Single : std_logic;
|
||||||
signal SS_Step : std_logic;
|
signal SS_Step : std_logic;
|
||||||
signal CountCycle : std_logic;
|
signal CountCycle : std_logic;
|
||||||
signal special : std_logic_vector(1 downto 0);
|
signal special : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
signal LIC_int : std_logic;
|
signal LIC_int : std_logic;
|
||||||
|
|
||||||
|
@ -212,8 +212,8 @@ begin
|
||||||
SS_Single => SS_Single
|
SS_Single => SS_Single
|
||||||
);
|
);
|
||||||
|
|
||||||
|
FIRQ_n_masked <= FIRQ_n or special(2);
|
||||||
NMI_n_masked <= NMI_n or special(1);
|
NMI_n_masked <= NMI_n or special(1);
|
||||||
FIRQ_n_masked <= FIRQ_n or special(1);
|
|
||||||
IRQ_n_masked <= IRQ_n or special(0);
|
IRQ_n_masked <= IRQ_n or special(0);
|
||||||
|
|
||||||
-- The CPU is slightly pipelined and the register update of the last
|
-- The CPU is slightly pipelined and the register update of the last
|
||||||
|
|
|
@ -100,7 +100,7 @@ architecture behavioral of MOS6502CpuMonCore is
|
||||||
signal SS_Step : std_logic;
|
signal SS_Step : std_logic;
|
||||||
signal SS_Step_held : std_logic;
|
signal SS_Step_held : std_logic;
|
||||||
signal CountCycle : std_logic;
|
signal CountCycle : std_logic;
|
||||||
signal special : std_logic_vector(1 downto 0);
|
signal special : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
signal memory_rd : std_logic;
|
signal memory_rd : std_logic;
|
||||||
signal memory_rd1 : std_logic;
|
signal memory_rd1 : std_logic;
|
||||||
|
|
|
@ -118,7 +118,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
|
||||||
signal SS_Step : std_logic;
|
signal SS_Step : std_logic;
|
||||||
signal SS_Step_held : std_logic;
|
signal SS_Step_held : std_logic;
|
||||||
signal CountCycle : std_logic;
|
signal CountCycle : std_logic;
|
||||||
signal special : std_logic_vector(1 downto 0);
|
signal special : std_logic_vector(2 downto 0);
|
||||||
signal skipNextOpcode : std_logic;
|
signal skipNextOpcode : std_logic;
|
||||||
|
|
||||||
signal Regs : std_logic_vector(255 downto 0);
|
signal Regs : std_logic_vector(255 downto 0);
|
||||||
|
|
|
@ -3,6 +3,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||||
|
|
||||||
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
|
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
|
||||||
|
|
|
@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
|
||||||
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
||||||
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
||||||
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
||||||
|
|
|
@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
|
||||||
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
||||||
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
||||||
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
||||||
|
|
|
@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
||||||
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
||||||
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
||||||
|
|
|
@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
|
||||||
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
||||||
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
||||||
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
||||||
|
|
|
@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
|
||||||
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
NET "Phi0" TNM_NET = clk_period_grp_phi0;
|
||||||
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
||||||
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
||||||
|
|
|
@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
||||||
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
||||||
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
||||||
|
|
|
@ -5,6 +5,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
|
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
|
||||||
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
|
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
|
||||||
NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3
|
NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
|
||||||
|
|
||||||
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
|
||||||
|
|
||||||
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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||||||
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NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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@ -3,6 +3,8 @@ TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
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||||||
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||||||
NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
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||||||
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||||||
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NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
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||||||
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||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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||||||
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||||||
#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW;
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||||||
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||||||
NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
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||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
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||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
NET "Addr<11>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
NET "Addr<11>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
||||||
NET "IRQ_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
NET "IRQ_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
||||||
|
|
|
@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "Addr<11>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
NET "Addr<11>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
||||||
NET "Addr<13>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
NET "Addr<13>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
|
||||||
|
|
||||||
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
|
|
|
@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
NET "NMI_n" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
NET "NMI_n" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
||||||
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
||||||
|
|
|
@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
|
||||||
|
|
||||||
|
NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||||
|
|
||||||
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
|
||||||
NET "Addr<12>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
NET "Addr<12>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
|
||||||
NET "Addr<13>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
NET "Addr<13>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
|
||||||
|
|
Loading…
Reference in New Issue
Block a user