All 6809 designs now use MC6809CpuMonCore

Change-Id: I97ca73690c7e1258a5b359260d695af25c21ca54
2019-10-24 14:06:03 +01:00 · 2019-10-24 14:06:03 +01:00 · c045ebd10c
parent ec577bda83
commit c045ebd10c
23 changed files with 1401 additions and 286 deletions
--- a/src/MC6809CpuMonALS.vhd
+++ b/src/MC6809CpuMonALS.vhd
@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6809CpuMonALS.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6809CpuMonALS
+--Device: XC6SLX9
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonALS is
+    generic (
+       ClkMult           : integer := 8;        -- default value correct for ALS
+       ClkDiv            : integer := 25;       -- default value correct for ALS
+       ClkPer            : real    := 20.0;     -- default value correct for ALS
+       num_comparators   : integer := 8;        -- default value correct for ALS
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for ALS
+       );
+    port (
+        clock            : in    std_logic;
+
+        --6809 Signals
+        BUSY             : out    std_logic;
+        E                : in     std_logic;
+        Q                : in     std_logic;
+        AVMA             : out    std_logic;
+        LIC              : out    std_logic;
+        TSC              : in     std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n            : in    std_logic;
+        NMI_n            : in    std_logic;
+        IRQ_n            : in    std_logic;
+        FIRQ_n           : in    std_logic;
+        HALT_n           : in    std_logic;
+        BS               : out   std_logic;
+        BA               : out   std_logic;
+        R_W_n            : out   std_logic_vector(1 downto 0);
+
+        Addr             : out   std_logic_vector(15 downto 0);
+        Data             : inout std_logic_vector(7 downto 0);
+
+        -- Level Shifers Controls
+        OERW_n           : out   std_logic;
+        OEAL_n           : out   std_logic;
+        OEAH_n           : out   std_logic;
+        OED_n            : out   std_logic;
+        DIRD             : out   std_logic;
+
+        -- External trigger inputs
+        trig             : in    std_logic_vector(1 downto 0);
+
+        -- ID/mode inputs
+        mode            : in    std_logic;
+        id              : in    std_logic_vector(3 downto 0);
+
+        -- Serial Console
+        avr_RxD          : in    std_logic;
+        avr_TxD          : out   std_logic;
+
+        -- GODIL Switches
+        sw_reset_n       : in    std_logic;
+        sw_interrupt_n   : in    std_logic;
+
+        -- GODIL LEDs
+        led_bkpt         : out   std_logic;
+        led_trig0        : out   std_logic;
+        led_trig1        : out   std_logic
+
+    );
+end MC6809CpuMonALS;
+
+architecture behavioral of MC6809CpuMonALS is
+
+    signal sw_reset      : std_logic;
+    signal sw_interrupt  : std_logic;
+    signal R_W_n_int     : std_logic;
+
+begin
+
+    sw_reset <= not sw_reset_n;
+    sw_interrupt <= not sw_interrupt_n;
+
+    wrapper : entity work.MC6809CpuMonCore
+      generic map (
+          UseCPU09Core      => true,
+          ClkMult           => ClkMult,
+          ClkDiv            => ClkDiv,
+          ClkPer            => ClkPer,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => '1',
+
+        -- 6809E Signals
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n_int,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_interrupt    => sw_interrupt,
+        sw_reset        => sw_reset,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => open,
+        tdin            => open,
+        tcclk           => open,
+
+        -- Debugging signals
+        test1           => open,
+        test2           => open
+    );
+
+    -- 6809 Outputs
+    R_W_n <= R_W_n_int & R_W_n_int;
+
+    -- Level Shifter Controls
+    OERW_n  <= TSC;
+    OEAH_n  <= TSC;
+    OEAL_n  <= TSC;
+    OED_n   <= TSC or not (Q or E);
+    DIRD    <= R_W_n_int;
+
+end behavioral;
--- a/src/MC6809CpuMonCore.vhd
+++ b/src/MC6809CpuMonCore.vhd
@ -1,5 +1,5 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
 --
 --------------------------------------------------------------------------------
 --   ____  ____
@ -7,12 +7,12 @@
 -- /___/  \  /
 -- \   \   \/
 --  \   \
--  /   /         Filename  : MC6808ECpuMon.vhd
-- /___/   /\     Timestamp : 02/07/2015
+--  /   /         Filename  : MC6808CpuMonCore.vhd
+-- /___/   /\     Timestamp : 24/010/2019
 -- \   \  /  \
 --  \___\/\___\
 --
--Design Name: MC6808ECpuMon
+--Design Name: MC6808CpuMonCore
 --Device: XC3S250E

 library ieee;
@ -21,37 +21,31 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use work.OhoPack.all ;

-entity MC6809ECpuMon is
+entity MC6809CpuMonCore is
    generic (
-       UseCPU09Core   : boolean := true;
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
+       UseCPU09Core      : boolean := true;
+       ClkMult           : integer := 10;       -- default value correct for GODIL
+       ClkDiv            : integer := 31;       -- default value correct for GODIL
+       ClkPer            : real    := 20.345;   -- default value correct for GODIL
+       num_comparators   : integer := 8;        -- default value correct for GODIL
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for GODIL
       );
    port (
-        clock49         : in    std_logic;
+        -- Fast clock
+        clock           : in    std_logic;

-        -- A locally generated test clock
-        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
-        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
-        clock_test      : out   std_logic;
-
-        -- 6809/6809E mode selection
-        -- Jumper is between pins B1 and D1
-        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
-        EMode_n         : in   std_logic;
+        -- Quadrature clocks
+        E               : in    std_logic;
+        Q               : in    std_logic;

        --6809 Signals
-        PIN33           : inout std_logic;
-        PIN34           : inout std_logic;
-        PIN35           : inout std_logic;
-        PIN36           : inout std_logic;
-        PIN38           : inout std_logic;
-        PIN39           : in    std_logic;
+        DMA_n_BREQ_n    : in   std_logic;
+
+        -- 6809E Sig
+        TSC             : in    std_logic;
+        LIC             : out   std_logic;
+        AVMA            : out   std_logic;
+        BUSY            : out   std_logic;

        -- Signals common to both 6809 and 6809E
        RES_n           : in    std_logic;
@ -73,14 +67,14 @@ entity MC6809ECpuMon is
        avr_RxD         : in    std_logic;
        avr_TxD         : out   std_logic;

-        -- GODIL Switches
-        sw1             : in    std_logic;
-        sw2             : in    std_logic;
+        -- Switches
+        sw_interrupt    : in    std_logic;
+        sw_reset        : in    std_logic;

-        -- GODIL LEDs
-        led3            : out   std_logic;
-        led6            : out   std_logic;
-        led8            : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;

        -- OHO_DY1 connected to test connector
        tmosi           : out   std_logic;
@ -92,9 +86,9 @@ entity MC6809ECpuMon is
        test2           : out   std_logic

    );
-end MC6809ECpuMon;
+end MC6809CpuMonCore;

-architecture behavioral of MC6809ECpuMon is
+architecture behavioral of MC6809CpuMonCore is

    signal clock_avr      : std_logic;

@ -132,22 +126,9 @@ architecture behavioral of MC6809ECpuMon is
    signal SS_Single      : std_logic;
    signal SS_Step        : std_logic;
    signal CountCycle     : std_logic;
-    signal special       : std_logic_vector(1 downto 0);
+    signal special        : std_logic_vector(1 downto 0);

-    signal clk_count      : std_logic_vector(1 downto 0);
-    signal quadrature     : std_logic_vector(1 downto 0);
-    signal LIC            : std_logic;
-    signal AVMA           : std_logic;
-    signal XTAL           : std_logic;
-    signal EXTAL          : std_logic;
-    signal MRDY           : std_logic;
-    signal TSC            : std_logic;
-    signal BUSY           : std_logic;
-    signal Q              : std_logic;
-    signal E              : std_logic;
-    signal DMA_n_BREQ_n   : std_logic;
-
-    signal clock7_3728    : std_logic;
+    signal LIC_int        : std_logic;

    signal E_a            : std_logic; -- E delayed by 0..20ns
    signal E_b            : std_logic; -- E delayed by 20..40ns
@ -161,24 +142,27 @@ architecture behavioral of MC6809ECpuMon is
    signal data_wr        : std_logic;
    signal nRSTout        : std_logic;

-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
    signal NMI_n_masked   : std_logic;
    signal IRQ_n_masked   : std_logic;
    signal FIRQ_n_masked  : std_logic;

+    signal led_trig0_n    : std_logic;
+    signal led_trig1_n    : std_logic;
+    signal led_bkpt_n     : std_logic;
+
 begin

-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
+    LIC     <= LIC_int;
+    -- The following outputs are not implemented
+    -- BUSY          (6809E mode)
+    BUSY    <= '0';
+
+    -- The following inputs are not implemented
+    -- DMA_n_BREQ_n  (6809 mode)
+
+    led_trig0 <= not led_trig0_n;
+    led_trig1 <= not led_trig1_n;
+    led_bkpt <= not led_bkpt_n;

    inst_dcm0 : entity work.DCM0
      generic map (
@ -187,14 +171,14 @@ begin
        ClkPer       => ClkPer
      )
      port map(
-        CLKIN_IN     => clock49,
+        CLKIN_IN     => clock,
        CLKFX_OUT    => clock_avr
      );

    mon : entity work.BusMonCore
      generic map (
-        num_comparators => 8,
-        avr_prog_mem_size => 1024 * 9
+        num_comparators => num_comparators,
+        avr_prog_mem_size => avr_prog_mem_size
      )
      port map (
        clock_avr    => clock_avr,
@ -220,11 +204,11 @@ begin
        lcd_db       => open,
        avr_RxD      => avr_RxD,
        avr_TxD      => avr_TxD,
-        sw1          => not sw_interrupt_n,
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
+        sw1          => sw_interrupt,
+        nsw2         => not sw_reset,
+        led3         => led_trig0_n,
+        led6         => led_trig1_n,
+        led8         => led_bkpt_n,
        tmosi        => tmosi,
        tdin         => tdin,
        tcclk        => tcclk,
@ -277,7 +261,7 @@ begin
            clk      => cpu_clk,
            rst      => not nRST_sync,
            vma      => AVMA,
-            lic_out  => LIC,
+            lic_out  => LIC_int,
            ifetch   => ifetch,
            opfetch  => open,
            ba       => BA,
@ -315,7 +299,7 @@ begin
    begin
        if rising_edge(cpu_clk) then
            if (hold = '0') then
-                ifetch1 <= ifetch and not LIC;
+                ifetch1 <= ifetch and not LIC_int;
            end if;
        end if;
    end process;
@ -375,41 +359,10 @@ begin

    memory_done <= memory_rd1 or memory_wr1;

-    -- The following outputs are not implemented
-    -- BUSY          (6809E mode)
-    BUSY    <= '0';
-
-    -- The following inputs are not implemented
-    -- DMA_n_BREQ_n  (6809 mode)
-
-    -- Pins whose functions are dependent on "E" mode
-    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
-    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
-
-    PIN34        <= 'Z'   when EMode_n = '0' else E;
-    E            <= PIN34 when EMode_n = '0' else quadrature(1);
-
-    PIN35        <= 'Z'   when EMode_n = '0' else Q;
-    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
-
-    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
-    MRDY         <= '1'   when EMode_n = '0' else PIN36;
-
-    PIN38        <= LIC   when EMode_n = '0' else 'Z';
-    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
-
-    TSC          <= PIN39 when EMode_n = '0' else '0';
-    XTAL         <= '0'   when EMode_n = '0' else PIN39;
-
-    -- A locally generated test clock
-    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
-    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
-    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
-
    -- Delayed/Deglitched version of the E clock
-    e_gen : process(clock49)
+    e_gen : process(clock)
    begin
-        if rising_edge(clock49) then
+        if rising_edge(clock) then
            E_a <= E;
            E_b <= E_a;
            if E_b /= E_i then
@ -440,42 +393,9 @@ begin
    -- Note: on the dragon this is not critical; setting to '1' seemed to work
    data_wr    <= Q or E;

-    -- Quadrature clock generator, unused in 6809E mode
-    quadrature_gen : process(EXTAL)
-    begin
-        if rising_edge(EXTAL) then
-            if (MRDY = '1') then
-                if (quadrature = "00") then
-                    quadrature <= "01";
-                elsif (quadrature = "01") then
-                    quadrature <= "11";
-                elsif (quadrature = "11") then
-                    quadrature <= "10";
-                else
-                    quadrature <= "00";
-                end if;
-            end if;
-        end if;
-    end process;
-
-    -- Seperate piece of circuitry that emits a 7.3728MHz clock
-
-    inst_dcm1 : entity work.DCM1 port map(
-        CLKIN_IN          => clock49,
-        CLK0_OUT          => clock7_3728,
-        CLK0_OUT1         => open,
-        CLK2X_OUT         => open
-    );
-
-    clk_gen : process(clock7_3728)
-    begin
-        if rising_edge(clock7_3728) then
-            clk_count <= clk_count + 1;
-        end if;
-    end process;
-
    -- Spare pins used for testing
    test1   <= E_a;
    test2   <= E_c;

+
 end behavioral;
--- a/src/MC6809CpuMonGODIL.vhd
+++ b/src/MC6809CpuMonGODIL.vhd
@ -0,0 +1,254 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6808CpuMonGODIL.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6808CpuMonGODIL
+--Device: XC3S250E/XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonGODIL is
+    generic (
+       LEDsActiveHigh    : boolean := false;    -- default value correct for GODIL
+       SW1ActiveHigh     : boolean := true;     -- default value correct for GODIL
+       SW2ActiveHigh     : boolean := false;    -- default value correct for GODIL
+       ClkMult           : integer := 10;       -- default value correct for GODIL
+       ClkDiv            : integer := 31;       -- default value correct for GODIL
+       ClkPer            : real    := 20.345;   -- default value correct for GODIL
+       num_comparators   : integer := 8;        -- default value correct for GODIL
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for GODIL
+       );
+    port (
+        clock49         : in    std_logic;
+
+        -- A locally generated test clock
+        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+        clock_test      : out   std_logic;
+
+        -- 6809/6809E mode selection
+        -- Jumper is between pins B1 and D1
+        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
+        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
+        EMode_n         : in   std_logic;
+
+        --6809 Signals
+        PIN33           : inout std_logic;
+        PIN34           : inout std_logic;
+        PIN35           : inout std_logic;
+        PIN36           : inout std_logic;
+        PIN38           : inout std_logic;
+        PIN39           : in    std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        IRQ_n           : in    std_logic;
+        FIRQ_n          : in    std_logic;
+        HALT_n          : in    std_logic;
+        BS              : out   std_logic;
+        BA              : out   std_logic;
+        R_W_n           : out   std_logic;
+
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- GODIL Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- GODIL LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic
+
+    );
+end MC6809CpuMonGODIL;
+
+architecture behavioral of MC6809CpuMonGODIL is
+
+    signal clk_count      : std_logic_vector(1 downto 0);
+    signal quadrature     : std_logic_vector(1 downto 0);
+
+    signal clock7_3728    : std_logic;
+
+    signal sw_reset       : std_logic;
+    signal sw_interrupt   : std_logic;
+    signal led_bkpt       : std_logic;
+    signal led_trig0      : std_logic;
+    signal led_trig1      : std_logic;
+
+    signal E              : std_logic;
+    signal Q              : std_logic;
+    signal DMA_n_BREQ_n   : std_logic;
+    signal MRDY           : std_logic;
+    signal TSC            : std_logic;
+    signal LIC            : std_logic;
+    signal AVMA           : std_logic;
+    signal BUSY           : std_logic;
+
+    signal XTAL           : std_logic;
+    signal EXTAL          : std_logic;
+
+begin
+
+    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
+    sw_interrupt <= sw1       when SW1ActiveHigh  else not sw1;
+    sw_reset     <= sw2       when SW2ActiveHigh  else not sw2;
+    led3         <= led_trig0 when LEDsActiveHigh else not led_trig0;
+    led6         <= led_trig1 when LEDsActiveHigh else not led_trig1;
+    led8         <= led_bkpt  when LEDsActiveHigh else not led_bkpt;
+
+    wrapper : entity work.MC6809CpuMonCore
+      generic map (
+          UseCPU09Core      => true,
+          ClkMult           => ClkMult,
+          ClkDiv            => ClkDiv,
+          ClkPer            => ClkPer,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock49,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => DMA_n_BREQ_n,
+
+        -- 6809E Sig
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_interrupt    => sw_interrupt,
+        sw_reset        => sw_reset,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => tmosi,
+        tdin            => tdin,
+        tcclk           => tcclk,
+
+        -- Debugging signals
+        test1           => test1,
+        test2           => test2
+    );
+
+    -- Pins whose functions are dependent on "E" mode
+    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
+    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
+
+    PIN34        <= 'Z'   when EMode_n = '0' else E;
+    E            <= PIN34 when EMode_n = '0' else quadrature(1);
+
+    PIN35        <= 'Z'   when EMode_n = '0' else Q;
+    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
+
+    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
+    MRDY         <= '1'   when EMode_n = '0' else PIN36;
+
+    PIN38        <= LIC   when EMode_n = '0' else 'Z';
+    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
+
+    TSC          <= PIN39 when EMode_n = '0' else '0';
+    XTAL         <= '0'   when EMode_n = '0' else PIN39;
+
+    -- A locally generated test clock
+    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
+
+    -- Quadrature clock generator, unused in 6809E mode
+    quadrature_gen : process(EXTAL)
+    begin
+        if rising_edge(EXTAL) then
+            if (MRDY = '1') then
+                if (quadrature = "00") then
+                    quadrature <= "01";
+                elsif (quadrature = "01") then
+                    quadrature <= "11";
+                elsif (quadrature = "11") then
+                    quadrature <= "10";
+                else
+                    quadrature <= "00";
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Seperate piece of circuitry that emits a 7.3728MHz clock
+    inst_dcm1 : entity work.DCM1 port map(
+        CLKIN_IN          => clock49,
+        CLK0_OUT          => clock7_3728,
+        CLK0_OUT1         => open,
+        CLK2X_OUT         => open
+    );
+
+    clk_gen : process(clock7_3728)
+    begin
+        if rising_edge(clock7_3728) then
+            clk_count <= clk_count + 1;
+        end if;
+    end process;
+
+end behavioral;
--- a/src/MultiBootLoader.v
+++ b/src/MultiBootLoader.v
@ -148,8 +148,8 @@ module MultiBootLoader
                 5'b11101: icap_din    = 16'hC000; // Z80 (mode = 1)
                 5'b01101: icap_din    = 16'hC000; // Z80 (mode = 0)
                 5'b01110: icap_din    = 16'h0000; // 65C02
-                 // 5'b11100: icap_din    = 16'h4000; // 6809 (mode = 1)
-                 // 5'b01100: icap_din    = 16'h4000; // 6809 (mode = 0)
+                 5'b11100: icap_din    = 16'h4000; // 6809 (mode = 1)
+                 5'b01100: icap_din    = 16'h4000; // 6809 (mode = 0)
                 default:  icap_din    = 16'h4000; // Unknown Adapter
               endcase

@ -174,8 +174,8 @@ module MultiBootLoader
                 5'b11101: icap_din    = 16'h030F; // Z80 (mode = 1)
                 5'b01101: icap_din    = 16'h030F; // Z80 (mode = 0)
                 5'b01110: icap_din    = 16'h0315; // 65C02
-                 // 5'b11100: icap_din    = 16'h031A; // 6809 (mode = 1)
-                 // 5'b01100: icap_din    = 16'h031A; // 6809 (mode = 0)
+                 5'b11100: icap_din    = 16'h031A; // 6809 (mode = 1)
+                 5'b01100: icap_din    = 16'h031A; // 6809 (mode = 0)
                 default:  icap_din    = 16'h0305; // Unknown Adapter
               endcase

--- a/target/godil_250/ice6809/Makefile
+++ b/target/godil_250/ice6809/Makefile
@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common

 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809ECpuMon
+PROJECT    = MC6809CpuMonGODIL

 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
--- a/target/godil_250/ice6809/ice6809.xise
+++ b/target/godil_250/ice6809/ice6809.xise
@ -18,17 +18,13 @@
    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
-    <file xil_pn:name="../../../src/MC6809ECpuMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
-    </file>
    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
    </file>
    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
@ -227,7 +223,7 @@
    </file>
    <file xil_pn:name="../../../src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
@ -241,6 +237,14 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
@ -256,7 +260,7 @@
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -270,7 +274,7 @@
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -350,9 +354,9 @@
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -410,7 +414,7 @@
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MC6809CpuMonGODIL" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -422,10 +426,10 @@
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809CpuMonGODIL_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809CpuMonGODIL_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809CpuMonGODIL_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809CpuMonGODIL_translate.vhd" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -445,7 +449,7 @@
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809CpuMonGODIL" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@ -549,7 +553,10 @@
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
  </properties>

-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/MC6809CpuMonGODIL" xil_pn:name="board.ucf"/>
+    <binding xil_pn:location="/MC6809CpuMonGODIL" xil_pn:name="memory.bmm"/>
+  </bindings>

  <libraries/>

--- a/target/godil_250/ice6809/memory.bmm
+++ b/target/godil_250/ice6809/memory.bmm
@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0

    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
        END_BUS_BLOCK;
-		  		  
+
    END_ADDRESS_SPACE;

 END_ADDRESS_MAP;
--- a/target/godil_250/icez80/icez80.xise
+++ b/target/godil_250/icez80/icez80.xise
@ -32,11 +32,11 @@
    </file>
    <file xil_pn:name="../../../src/T80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    </file>
    <file xil_pn:name="../../../src/T80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    </file>
    <file xil_pn:name="../../../src/T80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
@ -44,7 +44,7 @@
    </file>
    <file xil_pn:name="../../../src/T80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
@ -60,7 +60,7 @@
    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
@ -72,7 +72,7 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
@ -92,7 +92,7 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
@ -124,7 +124,7 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
@ -156,11 +156,11 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
@ -168,15 +168,15 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
@ -192,11 +192,11 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
@ -208,19 +208,19 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
@ -228,34 +228,34 @@
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    </file>
    <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
--- a/target/godil_500/ice6809/Makefile
+++ b/target/godil_500/ice6809/Makefile
@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common

 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809ECpuMon
+PROJECT    = MC6809CpuMonGODIL

 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
--- a/target/godil_500/ice6809/ice6809.xise
+++ b/target/godil_500/ice6809/ice6809.xise
@ -18,17 +18,13 @@
    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
-    <file xil_pn:name="../../../src/MC6809ECpuMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
-    </file>
    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
    </file>
    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
@ -227,7 +223,7 @@
    </file>
    <file xil_pn:name="../../../src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
@ -241,6 +237,14 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
@ -350,9 +354,9 @@
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -410,7 +414,7 @@
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -422,10 +426,10 @@
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -445,7 +449,7 @@
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
--- a/target/godil_500/ice6809/memory.bmm
+++ b/target/godil_500/ice6809/memory.bmm
@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0

    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
        END_BUS_BLOCK;
-		  		  
+
    END_ADDRESS_SPACE;

 END_ADDRESS_MAP;
--- a/target/godil_500/ipcore/WatchEvents.xise
+++ b/target/godil_500/ipcore/WatchEvents.xise
@ -30,7 +30,6 @@

  <properties>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
--- a/target/lx9_dave/gen_mcs.sh
+++ b/target/lx9_dave/gen_mcs.sh
@ -3,7 +3,6 @@

 # The S25FL032P has space for ~12 designs if they are uncompressed
 #
-#-u 1A4000                                       \
 #-u 1F8000                                       \
 #-u 24C000                                       \
 #-u 2A0000                                       \
@ -23,6 +22,7 @@ promgen                                          \
 -u  A8000 ice6502/ice6502.bit                   \
 -u  FC000 icez80/icez80.bit                     \
 -u 150000 ice65c02/ice65c02.bit                 \
+ -u 1A4000 ice6809/ice6809.bit                   \
 -o $NAME.mcs  -p mcs -w -spi -s 8192

 rm -f $NAME.cfi $NAME.prm
--- a/target/lx9_dave/ice6809/Makefile
+++ b/target/lx9_dave/ice6809/Makefile
@ -0,0 +1,18 @@
+# The root directory of the project
+ROOT       = ../../..
+
+# The common directory for makefile includes, etc.
+COMMON     = ../../common
+
+# The project .bit file produced by the Xilinx .xise project
+PROJECT    = MC6809CpuMonALS
+
+# The target .bit file to be generated including the monitor program
+TARGET     = ice6809
+
+# Frequuency that the AVR runs at
+F_CPU      = 16000000
+
+# Common include files
+include $(COMMON)/Makefile_$(TARGET).inc
+include $(COMMON)/Makefile.inc
--- a/target/lx9_dave/ice6809/board.ucf
+++ b/target/lx9_dave/ice6809/board.ucf
@ -0,0 +1,78 @@
+NET "clock" TNM_NET = clk_period_grp_50;
+TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
+
+NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "clock"          LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+
+#NET "VSS"           LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
+NET "NMI_n"          LOC="P79"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
+NET "IRQ_n"          LOC="P78"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
+NET "FIRQ_n"         LOC="P80"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
+NET "BS"             LOC="P40"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
+NET "BA"             LOC="P34"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
+#NET "VCC"           LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
+NET "Addr<0>"        LOC="P22"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
+NET "Addr<1>"        LOC="P23"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
+NET "Addr<2>"        LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
+NET "Addr<3>"        LOC="P21"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
+NET "Addr<4>"        LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
+NET "Addr<5>"        LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
+NET "Addr<6>"        LOC="P12"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
+NET "Addr<7>"        LOC="P14"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
+NET "Addr<8>"        LOC="P6"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
+NET "Addr<9>"        LOC="P7"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
+NET "Addr<10>"       LOC="P5"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
+NET "Addr<11>"       LOC="P1"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
+NET "Addr<12>"       LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
+
+NET "Addr<13>"       LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
+NET "Addr<14>"       LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
+NET "Addr<15>"       LOC="P2"   | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
+NET "Data<7>"        LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
+NET "Data<6>"        LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
+NET "Data<5>"        LOC="P99"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
+NET "Data<4>"        LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
+NET "Data<3>"        LOC="P97"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
+NET "Data<2>"        LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
+NET "Data<1>"        LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
+NET "Data<0>"        LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
+NET "R_W_n<0>"       LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
+NET "R_W_n<1>"       LOC="P30"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
+NET "BUSY"           LOC="P33"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
+NET "E"              LOC="P83"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
+NET "Q"              LOC="P82"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
+NET "AVMA"           LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
+NET "RES_n"          LOC="P81"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
+NET "LIC"            LOC="P43"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
+NET "TSC"            LOC="P74"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
+NET "HALT_n"         LOC="P75"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
+
+# Output Enables
+NET "OERW_n"         LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OEAH_n"         LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OEAL_n"         LOC="P10"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OED_n"          LOC="P92"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DIRD"           LOC="P93"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# LEDs and Switches
+NET "led_bkpt"       LOC="P44"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
+NET "led_trig0"      LOC="P41"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
+NET "led_trig1"      LOC="P67"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
+NET "sw_reset_n"     LOC="P45"  | IOSTANDARD = LVCMOS33 | PULLUP                  ; # reset
+NET "sw_interrupt_n" LOC="P66"  | IOSTANDARD = LVCMOS33 | PULLUP                  ; # interrupt
+
+# ID/Jumper
+NET "mode"           LOC="P140" | IOSTANDARD = LVCMOS33 | PULLUP                  ; # mode jumper
+NET "id<0>"          LOC="P88 " | IOSTANDARD = LVCMOS33 | PULLUP                  ; # id links
+NET "id<1>"          LOC="P87 " | IOSTANDARD = LVCMOS33 | PULLUP                  ; # id links
+NET "id<2>"          LOC="P85"  | IOSTANDARD = LVCMOS33 | PULLUP                  ; # id links
+NET "id<3>"          LOC="P84"  | IOSTANDARD = LVCMOS33 | PULLUP                  ; # id links
+
+# UART
+NET "avr_TxD"        LOC="P51"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "avr_RxD"        LOC="P55"  | IOSTANDARD = LVCMOS33                           ;
+
+# External trigger inputs
+NET "trig<0>"        LOC="P116" | IOSTANDARD = LVCMOS33                           ;
+NET "trig<1>"        LOC="P123" | IOSTANDARD = LVCMOS33                           ;
--- a/target/lx9_dave/ice6809/ice6809.xise
+++ b/target/lx9_dave/ice6809/ice6809.xise
@ -0,0 +1,613 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+    </file>
+    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+    </file>
+    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+    </file>
+    <file xil_pn:name="../ipcore/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerLatch.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+    </file>
+    <file xil_pn:name="../../../src/SYS09/cpu09l.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+    </file>
+    <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+    </file>
+    <file xil_pn:name="../../../src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+    </file>
+    <file xil_pn:name="../../../src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonALS.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+    </file>
+    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonALS|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonALS.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonALS" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MC6809CpuMonALS" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809CpuMonALS_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809CpuMonALS_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809CpuMonALS_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809CpuMonALS_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809CpuMonALS" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="MC6809CpuMonALS" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-23T12:17:55" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="614C752717807585A7E3847C608873AC" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/MC6809CpuMonALS" xil_pn:name="board.ucf"/>
+    <binding xil_pn:location="/MC6809CpuMonALS" xil_pn:name="memory.bmm"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
--- a/target/lx9_dave/ice6809/memory.bmm
+++ b/target/lx9_dave/ice6809/memory.bmm
@ -0,0 +1,42 @@
+ADDRESS_MAP avrmap PPC405 0
+
+    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+        END_BUS_BLOCK;
+
+    END_ADDRESS_SPACE;
+
+END_ADDRESS_MAP;
--- a/target/lx9_jason/ice6809/Makefile
+++ b/target/lx9_jason/ice6809/Makefile
@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common

 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809ECpuMon
+PROJECT    = MC6809CpuMonGODIL

 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
--- a/target/lx9_jason/ice6809/ice6809.xise
+++ b/target/lx9_jason/ice6809/ice6809.xise
@ -18,17 +18,13 @@
    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
-    <file xil_pn:name="../../../src/MC6809ECpuMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
-    </file>
    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
    </file>
    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
@ -227,7 +223,7 @@
    </file>
    <file xil_pn:name="../../../src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
@ -241,6 +237,14 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
@ -364,9 +368,9 @@
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -435,7 +439,7 @@
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -450,10 +454,10 @@
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -477,7 +481,7 @@
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
--- a/target/lx9_jason/ice6809/memory.bmm
+++ b/target/lx9_jason/ice6809/memory.bmm
@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0

    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
        END_BUS_BLOCK;
-		  		  
+
    END_ADDRESS_SPACE;

 END_ADDRESS_MAP;
--- a/target/lx9_jason_flipped/ice6809/Makefile
+++ b/target/lx9_jason_flipped/ice6809/Makefile
@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common

 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809ECpuMon
+PROJECT    = MC6809CpuMonGODIL

 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
--- a/target/lx9_jason_flipped/ice6809/ice6809.xise
+++ b/target/lx9_jason_flipped/ice6809/ice6809.xise
@ -18,17 +18,13 @@
    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
-    <file xil_pn:name="../../../src/MC6809ECpuMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
-    </file>
    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
    </file>
    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
@ -227,7 +223,7 @@
    </file>
    <file xil_pn:name="../../../src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
    </file>
    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
@ -241,6 +237,14 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+    </file>
+    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    </file>
    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
@ -272,7 +276,7 @@
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -364,9 +368,9 @@
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -435,7 +439,7 @@
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -450,10 +454,10 @@
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -477,7 +481,7 @@
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
--- a/target/lx9_jason_flipped/ice6809/memory.bmm
+++ b/target/lx9_jason_flipped/ice6809/memory.bmm
@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0

    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
        END_BUS_BLOCK;

        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
        END_BUS_BLOCK;
-		  		  
+
    END_ADDRESS_SPACE;

 END_ADDRESS_MAP;